Device and method for driving address electrode of surface discharge type plasma display panel

ABSTRACT

The present invention relates to a technique for driving a surface discharge type plasma display panel, and more particularly, it is an object of the present invention to freely perform setting without increasing a rating required for an IC having an address driver when a high voltage is to be output from an address electrode for a priming discharge period and a sustain discharge period. In order to attain the above-mentioned object, if the same voltage is simultaneously output to all address electrodes switches are turned off and on in a circuit respectively and a cathode of a diode and an anode of a diode are conducted. Then, the switches are forcedly turned off and on, respectively. In a circuit switches are turned on and off respectively and a voltage Va 2  is substantially applied to all the address electrodes through the diode.

TECHNICAL FIELD

The present invention relates to a surface discharge type plasma displaypanel and more particularly to a technique for driving an addresselectrode thereof.

DISCUSSION OF THE BACKGROUND

FIG. 56 is a circuit diagram showing a state of address electrodedriving of a surface discharge type plasma display panel. Scanelectrodes X and Y_(k) intersect an address electrode A_(j) for onedisplay cell C_(jk) of the surface discharge type plasma display panel(j, k=1, 2 . . . ).

In such a surface discharge type plasma display panel, there hasconventionally been proposed a technique that a negative pulse is notgiven to the scan electrode Y_(k) but a great positive pulse is given tothe address electrode A_(j) when performing a so-called “primingdischarge” in which a history in the display cell C_(jk) is erased and aspace charge is left. The reason is that a positive pulse can begenerated more simply and easily than a negative pulse.

A high voltage generating circuit AD1 and an address drive circuit AD2for switching an output of the high voltage generating circuit AD1 or aground potential and for outputting the same to the address electrodeA_(j) are provided corresponding to the address electrode A_(j). Theaddress drive circuit AD2 comprises switches SW3 and SW4 which areconnected in series between the output of the high voltage generatingcircuit AD1 and the ground potential, and diodes D3 and D4 connected inparallel with the switches SW3 and SW4 respectively.

The scan electrode X is provided with a drive circuit SD3 for generatinga voltage to be applied to the scan electrode X. Furthermore, a scanningdrive circuit SD1 and a switch circuit SD2 for switching an output ofthe scanning drive circuit SD1 or a ground potential and for outputtingthe same to each scan electrode Y_(k) are provided corresponding to thescan electrode Y_(k).

Such a structure has been described in Japanese Patent Laid-open No.P07-160218A, for example, in which the high voltage generating circuitAD1 and the address drive circuit AD2 are indicated as the referencenumerals 233 a and 233 bj, respectively.

To the address electrode A_(j) are respectively applied a voltage Vawfor a priming discharge for write preparation (“a reset period”described in the Japanese Patent Laid-open No. P07-160218A), a voltageVa for a write discharge (“an address period” described in the JapanesePatent Laid-open No. P07-160218A) and a voltage Vaw for a sustaindischarge period (“a sustain discharge period” described in the JapanesePatent Laid-open No. P07-160218A).

For the reset period and the sustain discharge period, a switch SW2 ofthe high voltage generating circuit AD1 is turned off and a switch SW1thereof is turned on so that a voltage Vas supported by a Zener diode isadded to the voltage Va supplied from a power source and a voltageVaw(=Va+Vas) is output from the high voltage generating circuit AD1.Then, the switches SW4 and SW3 of the address drive circuit AD2 for allthe address electrodes A_(j) are turned off and on, respectively.Consequently, the voltage Vaw is supplied to all the address electrodesA_(j).

However, a rated voltage of an IC constituting the high voltagegenerating circuit AD1 and the address drive circuit AD2 should be setequal to or higher than a maximum value of a voltage to be used in theabove-mentioned procedure. For this reason, the rated voltage of the ICshould be equal to or higher than the voltage Vaw(=Va+Vas) which ishigher than the voltage Va required for the write discharge and isrequired for the sustain discharge period.

More specifically, an IC having a high breakdown voltage is required tooutput a high voltage for the reset period and the sustain dischargeperiod. As a result, a cost is increased. Moreover, since the voltagesto be output for the reset period and the sustain discharge period arealso influenced by the performance of the IC, a value thereof islimited.

In a conventional method, furthermore, in the case where the switch SW3on a high arm of the address drive circuit AD2 is turned on to output“H” for the write discharge period, a current sometimes flows into theaddress electrode A_(j) in a suction direction by the output of the scanelectrodes X and Y_(k).

FIG. 57 is a circuit diagram showing, in detail, a structure of theaddress drive circuit AD2 illustrated in FIG. 56, in which the displaycell C_(jk) is replaced by an electrically equivalent circuit. Thereexists an equivalent capacitor CP between the scan electrode Y_(k) andthe address electrode A_(j). Similarly, the equivalent capacitors existbetween the scan electrode X and the address electrode A_(j) and betweenthe scan electrode X and the scan electrode Y_(k). The switches SW3 andSW4 of the address drive circuit AD2 are implemented by MOS transistorsT1 and T2, respectively.

The address drive circuit AD2 gives “H” to the address electrode A_(j)so that the equivalent capacitor CP is charged. With such charging kept,switches SW5 and SW6 are turned on and off in the switch circuit SD2 forthe sustain discharge period, respectively. When the voltage of the scanelectrode Y_(k) is changed to “H”, the electric potential of the addresselectrode A_(j) tries to perform step-up by the equivalent capacitor CP.At this time, the diode D3 of the address drive circuit AD2 causes acurrent to flow to the power source side for supplying the electricpotential Va, thereby preventing the step-up of the voltage.

In this case, if the MOS, transistors T1 and T2 constituting the addressdrive circuit AD2 are not formed by using a dielectric isolating methodbut a self-isolating technique, a parasitic transistor is generated.Consequently, the following problem arises.

FIG. 58 is a sectional view showing structures of the MOS transistors T1and T2 formed by using the self-isolating technique. A PNP transistor T3is parasitic on the PMOS transistor T1, and a base current of theparasitic transistor flows with a rise in the electric potential of theaddress electrode A_(j). Consequently, a short-circuit current 12 flowsfrom the power source for supplying the electric potential Va to aground through the transistors T1 and T3. Therefore, there is apossibility that the address drive circuit AD2 might be subjected to athermal breakdown.

SUMMARY OF THE INVENTION

A first aspect of an address electrode driving apparatus for driving anaddress electrode for a surface discharge type plasma display panelhaving a plurality of scan electrodes, a plurality of address electrodeswhich are orthogonal to the scan electrodes, and a display cell formedon each of intersecting points of the scan electrodes and the addresselectrodes, in accordance with the present invention, is that theapparatus comprises a plurality of drive circuits including a firstnumber of output stages, each output stage having an output terminalprovided corresponding to each of the address electrodes and connectedthereto, and a first input terminal and a second input terminal, one ofwhich is selectively connected to the output terminal, a first powercontrol circuit for supplying, to the second input terminal, one of areference potential and a first electric potential which is higher thanthe reference potential, and a second power control circuit forsupplying, to the first input terminal, a second electric potentialwhich is lower than the first electric potential and is higher than thereference potential or connecting the first input terminal to the secondinput terminal.

A second aspect of the address electrode driving apparatus in accordancewith the present invention is that the apparatus of the first aspectfurther comprises a control circuit for outputting drive data whichserves to set the output terminal of the drive circuit to be connectedto the first input terminal or the second input terminal, and aplurality of transmitting circuits provided corresponding to each of theaddress electrodes for transmitting the drive data for the correspondingaddress electrodes. Each of the transmitting circuits includes a firstbuffer having an input terminal for inputting the drive data and anoutput terminal for transmitting the drive data, being connected to afirst reference potential point for supplying the reference potentialand a first electric potential point for supplying a first sourcepotential which is higher than the reference potential and is lower thanthe second electric potential, and receiving operating power therefrom,a capacitor having one of terminals connected to the output terminal ofthe first buffer and the other terminal, and a second buffer having aninput terminal connected to the other terminal of the capacitor and anoutput terminal connected to a corresponding one of the drive circuits,being connected to the second input terminal and a second electricpotential point, and receiving operating power therefrom.

A third aspect of the address electrode driving apparatus in accordancewith the present invention is that in the apparatus of the secondaspect, each of the drive circuits further includes a protective diodehaving a cathode connected to a corresponding one of the addresselectrodes and an anode connected to the second input terminal.

A fourth aspect of the address electrode driving apparatus in accordancewith the present invention is that the apparatus of the third aspectfurther comprises a third electric potential point to be connected toone of a fourth electric potential point to which a second sourcepotential is supplied and the second input terminal. Each of thetransmitting circuits further includes a first diode having an anodeconnected to the first reference potential point and a cathode connectedto the terminal of the capacitor, and a second diode having an anodeconnected to the other terminal of the capacitor and a cathode connectedto the third electric potential point, and the second buffer furtherincludes a protective diode having a cathode connected to the otherterminal of the capacitor and an anode connected to the second inputterminal.

A fifth aspect of the address electrode driving apparatus in accordancewith the present invention is that in the apparatus of the fourthaspect, the second electric potential point is the third electricpotential point.

A sixth aspect of the address electrode driving apparatus in accordancewith the present invention is that in the apparatus of the fourthaspect, the second electric potential point is the fourth electricpotential point.

A seventh aspect of the address electrode driving apparatus inaccordance with the present inventions is that in the apparatus of thefourth aspect, each of the transmitting circuits further includes athird diode having an anode connected to the terminal of the capacitorand a cathode connected to the first electric potential point.

An eighth aspect of the address electrode driving apparatus inaccordance with the present invention is that in the apparatus of theseventh aspect, the second electric potential point is the thirdelectric potential point.

A ninth aspect of the address electrode driving apparatus in accordancewith the present invention is that in the apparatus of the seventhaspect, the second electric potential point is the fourth electricpotential point.

A tenth aspect of the address electrode driving apparatus in accordancewith the present invention is that in the apparatus of the fourthaspect, the first buffer further includes a protective diode having ananode connected to the terminal of the capacitor and a cathode connectedto the first electric potential point.

An eleventh aspect of the address electrode driving apparatus inaccordance with the present invention is that the apparatus of thefourth aspect further comprises a diode having an anode connected to thefourth electric potential point and a cathode, and a capacitor connectedbetween the cathode of the diode and a second reference potential pointacting as a reference of a second source potential to be applied to thefourth electric potential point. The third electric potential point isconnected to the fourth electric potential point through the diode.

A twelfth aspect of the address electrode driving apparatus inaccordance with the present invention is that the apparatus of thesecond aspect further comprises a control circuit for outputting drivedata which serves to set the output terminal of the drive circuit to beconnected to the first input terminal or the second input terminal, anda plurality of transmitting circuits provided corresponding to each ofthe address electrodes for transmitting the drive data for thecorresponding address electrodes. Each of the transmitting circuitsincludes a first buffer having an input terminal for inputting the drivedata and an output terminal for transmitting the drive data, beingconnected to a first reference potential point for supplying thereference potential and a first electric potential point for supplying afirst source potential which is higher than the reference potential andis lower than the second electric potential, and receiving operatingpower therefrom, a diode having an anode connected to the outputterminal of the first buffer and a cathode, and a second buffer havingan input terminal connected to the cathode of the diode and an outputterminal connected to a corresponding one of the drive circuits, beingconnected to the second input terminal and a second electric potentialpoint, and receiving operating power therefrom.

A thirteenth aspect of the address electrode driving apparatus inaccordance with the present invention is that in the apparatus of thetwelfth aspect, each of the transmitting circuits further includes aresistor provided between the cathode of the diode and the second inputterminal.

A fourteenth aspect of the address electrode driving apparatus inaccordance with the present invention is that in the apparatus of thesecond aspect, the drive circuits further include a second number ofdata input terminals for inputting the second number of drive data, andthe second number of data output terminals for shifting out data givento the data input terminals, and a third number of drive circuits make aset and are connected in series with respect to the data input terminalsand the data output terminals.

A fifteenth aspect of the address electrode driving apparatus inaccordance with the present invention is that in the apparatus of thefourteenth aspect, the set of drive circuits have a timing in which thedrive data is shifted out from the data input terminal to the dataoutput terminal and a timing in which the drive data given to the datainput terminal is latched, the timings being divided into two classeswhich are different from each other.

A sixteenth aspect of the address electrode driving apparatus inaccordance with the present invention is that in the apparatus of thefirst aspect, the surface discharge type plasma display panel furtherincludes a plurality of other scan electrodes which are orthogonal tothe address electrodes, and a predetermined electric potential isapplied to the other scan electrodes through a pair of diodes connectedin antiparallel with each other.

A first aspect of an address electrode driving method in accordance withthe present invention is that the method is applied to a plasma displaysystem comprising a surface discharge type plasma display panelincluding a plurality of scan electrodes, a plurality of addresselectrodes which are orthogonal to the scan electrodes, and a displaycell formed on each of intersecting points of the scan electrodes andthe address electrodes, a plurality of drive circuits including a firstnumber of output stages, each output stage having an output terminalprovided corresponding to each of the address electrodes and connectedthereto, and a first input terminal and a second input terminal, one ofwhich is selectively connected to the output terminal, a plurality ofdrive circuits provided corresponding to the address electrodes, each ofwhich has an output terminal connected to a corresponding one of theaddress electrodes and a first input terminal and a second inputterminal, one of which is selectively connected to the output terminal,a control circuit for outputting drive data which serves to set theoutput terminal of the drive circuit to be connected to the first inputterminal or the second input terminal, a first power control circuit forsupplying, to the second input terminal, one of a reference potentialand a first electric potential which is higher than the referencepotential, a second power control circuit for supplying, to the firstinput terminal, a second electric potential which is lower than thefirst electric potential and is higher than the reference potential, orfor connecting the first input terminal to the second input terminal, afirst buffer having an input terminal provided corresponding to each ofthe address electrodes for inputting the drive data for thecorresponding address electrodes, an output terminal for transmittingthe drive data, and an output stage having a push-pull structure whichis connected in series between a first reference potential point forsupplying the reference potential and a first electric potential pointfor supplying a first source potential which is higher than thereference potential and is lower than the second electric potential, acapacitor having one of terminals connected to the output terminal ofthe first buffer and the other terminal, a second buffer having an inputterminal connected to the other terminal of the capacitor, an outputterminal connected to a corresponding one of the drive circuits, and aninput stage having a push-pull structure which is connected in seriesbetween the second input terminal and a second electric potential point,a first diode having an anode connected to the first reference potentialpoint and a cathode connected to the terminal of the capacitor, and asecond diode having a cathode connected to the second electric potentialpoint and an anode connected to the other terminal of the capacitor. Themethod comprises the steps of (a) for a write preparation period, (a-1)connecting the second electric potential point to the second inputterminal, (a-2) connecting the first input terminal to the second inputterminal by the second power control circuit, and (a-3) supplying thefirst electric potential to the second input terminal by the first powercontrol circuit, and then supplying the reference potential, (b) for awrite discharge period, (b-1) connecting the second input terminal tothe first reference potential point by the first power control circuit,(b-2) supplying the first source potential to the second electricpotential point, (b-3) supplying the second electric potential to thefirst input terminal by the second power control circuit, and (b-4)connecting an output terminal of each of the drive circuits to one ofthe first input terminal and the second input terminal based on thedrive data, and (c) after the write discharge period and before asustain discharge period, (c-1) connecting the second input terminal tothe first reference potential point by the first power control circuit,(c-2) connecting the second electric potential point to the second inputterminal, (c-3) connecting the first input terminal to the second inputterminal by the second power control circuit, and (c-4) forcedly settingthe drive data to a reference potential.

A second aspect of the address electrode driving method in accordancewith the present invention is that the method of the first aspectfurther comprises the step of (a-4) forcedly setting the drive data to“H” prior to the step (a-3) for the write preparation period.

A third aspect of the address electrode driving method in accordancewith the present invention is that the method of the second aspectfurther comprises the step of (d) forcedly setting the drive data to “L”after the write preparation period and before the write dischargeperiod.

A fourth aspect of an address electrode driving method in accordancewith the present invention is that the method is applied to a plasmadisplay system comprising a surface discharge type plasma display panelincluding a plurality of scan electrodes, a plurality of addresselectrodes which are orthogonal to the scan electrodes, and a displaycell formed on each of intersecting points of the scan electrodes andthe address electrodes, a plurality of drive circuits including anoutput terminal provided corresponding to each of the address electrodesand connected to a corresponding one of the address electrodes, and afirst input terminal and a second input terminal, one of which isselectively connected to the output terminal, a control circuit foroutputting drive data which serves to set the output terminal of thedrive circuit to be connected to the first input terminal or the secondinput terminal, a first power control circuit for supplying one of areference potential and a first electric potential which is higher thanthe reference potential to the second input terminal, and a second powercontrol circuit for supplying, to the first input terminal, a secondelectric potential which is lower than the first electric potential andis higher than the reference potential or connecting the first inputterminal to the second input terminal, a first buffer having an inputterminal provided corresponding to each of the address electrodes forinputting the drive data for the corresponding address electrodes, anoutput terminal for transmitting the drive data, and an output stagehaving a push-pull structure which is connected in series between afirst reference potential point for supplying the reference potentialand a first electric potential point for supplying a first sourcepotential that is higher than the reference potential and is lower thanthe second electric potential, a diode having an anode connected to theoutput terminal of the first buffer and a cathode, a second bufferhaving an input terminal connected to the cathode of the diode, anoutput terminal connected to a corresponding one of the drive circuits,and an input stage having a push-pull structure which is connected inseries between the second input terminal and a second electric potentialpoint, and a resistor connected to the second input terminal and theinput terminal of the second buffer. The method comprises the steps of(a) for a write preparation period, (a-1) connecting the first inputterminal to the second input terminal by the second power controlcircuit, and (a-2) supplying the first electric potential to the secondinput terminal by the first power control circuit, and then supplyingthe reference potential, (b) for a write discharge period, (b-1)connecting the second input terminal to the first reference potentialpoint by the first power control circuit, (b-2) supplying the secondelectric potential to the first input terminal by the second powercontrol circuit, and (b-3) connecting the output terminals of the drivecircuits to one of the first input terminal and the second inputterminal based on the drive data, and (c) after the write dischargeperiod and before a sustain discharge period, (c-1) connecting thesecond input terminal to the first reference potential point by thefirst power control circuit, and (c-2) connecting the first inputterminal to the second input terminal by the second power controlcircuit.

According to the first aspect of the address electrode driving apparatusin accordance with the present invention, the first power controlcircuit can supply the reference potential to the second input terminal,and the second power control circuit can supply the first electricpotential to the first input terminal. By selectively connecting theoutput terminal to the first input terminal or the second input terminalin the drive circuit, therefore, a write discharge can be performed forthe address electrode in a desirable pattern. On the other hand, thefirst power control circuit supplies the first electric potential to thesecond input terminal and the second power control circuit connects thefirst input terminal to the second input terminal and short-circuits thesecond input terminal and the output terminal of the drive circuit.Consequently, it is possible to supply the second electric potential toall the address electrodes at once without requiring a breakdown voltagefor the second electric potential in the drive circuit. Thus, aself-erase discharge for write preparation can be performed.

According to the second aspect of the address electrode drivingapparatus in accordance with the present invention, two buffers fortransferring the drive data are employed. The first buffer is isolatedfrom the second input terminal of the drive circuit by the capacitor.Accordingly, even if the first power control circuit supplies the firstelectric potential to the second input terminal of the drive circuit,the first buffer is isolated from the first electric potential.Consequently, the control circuit can also be protected.

According to the third aspect of the address electrode driving apparatusin accordance with the present invention, in the case where the firstelectric potential is applied to the second input terminal, it is givento the address electrode through the protective diode. Consequently, theself-erase discharge can be caused.

According to the fourth to sixth aspects of the address electrodedriving apparatus in accordance with the present invention, thecapacitor charged by application of the first electric potential to thesecond input terminal can be discharged by supplying the referencepotential to the second input terminal and connecting the third electricpotential point to the second input terminal by means of the first powercontrol circuit. At the time of the write discharge, even if the firstbuffer is changed between “L” and “H”, the charge and discharge of thecapacitor can be quickly performed by supplying the reference potentialto the second input terminal and connecting the fourth electricpotential point to the third electric potential point by means of thefirst power control circuit. Therefore, the drive data can betransmitted to the second buffer. Furthermore, after the write dischargeis completed, the first power control circuit supplies the referencepotential to the second input terminal and connects the first referencepotential point to the third electric potential point, therebydischarging the capacitor whether the first buffer outputs “L” to chargethe capacitor or outputs “H” to charge the capacitor. Consequently, asustain discharge is not affected.

According to the seventh to tenth aspects of the address electrodedriving apparatus in accordance with the present invention, in the casewhere the first electric potential is to be applied to the addresselectrode, the first buffer can be protected from the step-up of avoltage caused by the capacitor even if the first buffer is caused tooutput “H” in order to rapidly rise.

According to the twelfth aspect of the address electrode drivingapparatus in accordance with the present invention, the electricpotential which is lower than the second source potential by a forwardvoltage of the diode is applied to the third electric potential point.Therefore, the capacitor is not charged based on the forward voltage ofthe second diode of the transmitting circuit.

According to the twelfth aspect of the address electrode drivingapparatus in accordance with the present invention, two buffers fortransferring the drive data are employed. Even if the first electricpotential is applied to the second input terminal, the diode isreversibly biased. Therefore, the first buffer is isolated from thefirst electric potential. Consequently, the control circuit can also beprotected.

According to the thirteenth aspect of the address electrode drivingapparatus in accordance with the present invention, even if H” is inputto the first buffer and the diode is forward biased to cause a forwardcurrent to flow when the self-erase discharge is completed, a magnitudeof the forward current can be limited by the resistor and the firstbuffer can be protected from a fluctuation in the electric potential ofthe second input terminal. Furthermore, if the drive data is changedfrom “H” to “L” for the write discharge period, electric charges held inan input capacity of the second buffer can be discharged through theresistor.

According to the fourteenth aspect of the address electrode drivingapparatus in accordance with the present invention, since it issufficient that the transmitting circuit transmits the drive data everythird number, a structure thereof can be simplified.

According to the fifteenth aspect of the address electrode drivingapparatus in accordance with the present invention, since it issufficient that the transmitting circuit transmits the drive data every2×the third number of output circuits, a structure thereof can furtherbe simplified.

According to the sixteenth aspect of the address electrode drivingapparatus in accordance with the present invention, the electricpotential of the other scan electrode is not raised above apredetermined electric potential even if it tries to perform step-up byan equivalent capacitor in the display cell.

According to the first aspect of the address electrode driving method inaccordance with the present invention, by the function of the capacitor,the second electric potential can be applied to all the addresselectrodes at once for the write preparation period without requiring abreakdown voltage for the second electric potential in the drivecircuit. Consequently, a self-erase discharge can be performed. Thecapacitor charged by a write discharge is discharged by the output stageof the first buffer and the second diode or by the input stage of thesecond buffer and the first diode at the step (c) before the sustaindischarge period.

According to the second aspect of the address electrode driving methodin accordance with the present invention, the capacitor can be chargedin advance to raise an electric potential on the other terminal above anelectric potential on the one of terminals. Therefore, it is possible toenhance a speed at which the second input terminal can rise to the firstelectric potential at the step (a-3).

According to the third aspect of the address electrode driving method inaccordance with the present invention, the capacitor charged at the step(a-4) is discharged. Consequently, it is possible to avoid affecting thewrite discharge period.

According to the fourth aspect of the address electrode driving methodin accordance with the present invention, by the function of the diode,the second electric potential can be supplied to all the addresselectrodes at once for the write preparation period without requiring abreakdown voltage for the second electric potential in the drivecircuit. Consequently, the self-erase discharge can be performed. By thefunction of the resistor, a current flowing in the first buffer means issuppressed if the drive data is changed from “L” to “H” for the writedischarge period, and electric charges stored in the input stage of thesecond buffer are discharged when the drive data is changed from “H” to“L”.

In order to solve the above-mentioned problems, it is an object of thepresent invention to freely set a high voltage output for a primingdischarge period and a sustain discharge period without increasing arating required for an IC having an address driver.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a basic thought of the presentinvention;

FIG. 2 is a block diagram showing a first embodiment of the presentinvention;

FIG. 3 is an enlarged view showing a state obtained in the vicinity ofone display cell C_(jk);

FIGS. 4 and 5 are circuit diagrams showing a state in which a digitalsignal generating circuit 21 is connected to other circuits;

FIG. 6 is a circuit diagram showing a structure of a part 31;

FIG. 7 is a circuit diagram showing a structure of a component 32 a of apart 32;

FIG. 8 is a circuit diagram showing a structure of a power controlcircuit 24;

FIG. 9 is a circuit diagram showing a structure of a power controlcircuit 25;

FIG. 10 is a circuit diagram showing a structure of a power controlcircuit 26;

FIG. 11 is a circuit diagram showing a structure of a gate circuit 7 fora push-pull driver;

FIG. 12 is a timing chart showing operation according to the firstembodiment of the present invention;

FIGS. 13 to 18 are circuit diagrams showing the operation according tothe first embodiment of the present invention;

FIG. 19 is a circuit diagram showing a structure of a component 32 b;

FIGS. 20 to 25 are circuit diagrams showing operation according to asecond embodiment of the present invention;

FIG. 26 is a circuit diagram showing a structure of a component 32 c;

FIG. 27 is a timing chart showing the operation according to the secondembodiment of the present invention;

FIGS. 28 to 33 are circuit diagrams showing operation according to athird embodiment of the present invention;

FIG. 34 is a circuit diagram showing a structure of a component 32 d;

FIGS. 35 to 40 are circuit diagrams showing operation according to afourth embodiment of the present invention;

FIG. 41 is a timing chart showing operation according to a fifthembodiment of the present invention;

FIGS. 42 and 43 are circuit diagrams showing the operation according tothe fifth embodiment of the present invention;

FIG. 44 is a circuit diagram showing a structure of a component 32 e;

FIG. 45 is a timing chart showing operation according to a sixthembodiment of the present invention;

FIGS. 46 to 49 are circuit diagrams showing the operation according tothe sixth embodiment of the present invention;

FIG. 50 is a circuit diagram showing a structure according to a seventhembodiment of the present invention;

FIGS. 51 and 52 are circuit diagrams showing a structure according to aneighth embodiment of the present invention;

FIG. 53 is a timing chart showing operation according to the eighthembodiment of the present invention;

FIG. 54 is a circuit diagram showing the structure according to theeighth embodiment of the present invention;

FIG. 55 is a timing chart showing the operation according to the eighthembodiment of the present invention;

FIGS. 56 and 57 are circuit diagrams showing the prior art; and

FIG. 58 is a sectional view showing the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior to description of the best mode, the technique of the presentinvention will be described briefly. FIG. 1 is a circuit diagramillustrating a basic thought of the present invention. The high voltagegenerating circuit AD1 and the drive circuit SD3 in the structure shownin FIG. 56 are replaced by a high voltage generating circuit AD0 and adrive circuit SDS, respectively.

The high voltage generating circuit AD0 includes power control circuitsDR0 and DR1. The power control circuit DR0 has switches SW10 and SW11and diodes DR10 and D11, and the power control circuit DR1 has switchesSW12 and SW13 and diodes D12 and D13.

The diode D13 has a cathode connected to a cathode of a diode D3 on ahigh arm side of an address drive circuit AD2, and an anode connected toan anode of a diode D4 on a low arm side of the address drive circuitAD2. The switch SW13 is connected in parallel with the diode D13. Thediode D12 has an anode connected to the cathode of the diode D3, and acathode to which an electric potential Va is applied. The switch SW12 isconnected in parallel with the diode D12.

The diode D10 has a cathode to which an electric potential Va2 isapplied, and an anode connected to the anode of the diode D4 and acathode of the diode D11. The diode D11 has an anode to which a groundpotential is applied. The switches SW10 and SW11 are provided inparallel with the diodes D10 and D11, respectively.

With a write discharge in which a voltage is output to an addresselectrode A_(j) based on individual drive data, the switches SW12 andSW13 are turned on and off in the circuit DR1 respectively, and a writedischarge voltage Va is applied to the cathode of the diode D3 of theaddress drive circuit AD2. On the other hand, the switches SW10 and SW11are turned off and on in the circuit DR0 respectively, and the groundpotential is applied to the anode of the diode D4 of the address drivecircuit AD2. Such an electric potential is applied to both terminals ofthe address drive circuit AD2. Therefore, the discharge voltage Va isapplied to the address electrode A_(j) when switches SW3 and SW4 areturned on and off, respectively. And the ground potential is applied tothe address electrode A_(j) when switches SW3 and SW4 are turned off andon, respectively.

For a reset period and a sustain discharge period in which the samevoltage is output to all address electrodes at the same time, theswitches SW12 and SW13 are turned off and on respectively to cause thecathode of the diode D3 and the anode of the diode D4 to be conducted.In this sequence, the switches SW3 and SW4 are forcedly turned off andon, respectively. In the circuit DR0, if the switches SW10 and SW11 areturned on and off respectively, the voltage Va2 is applied to the anodeof the diode D4 and is substantially applied to all the addresselectrodes through the diode D4. Furthermore, in the case where theswitches SW10 and S11 are turned off and on respectively, electriccharges stored in all the address electrodes are discharged to theswitch SW11 through the switch SW4, the switch SW13 and the diode D3.

By the above-mentioned operation, a rating of an IC having the addressdrive circuit AD2 which withstands the write discharge voltage Va isenough and the high voltage Va2 for the priming discharge period and thesustain discharge period can freely be set.

For the sustain discharge period, even if a voltage of a scan electrodeY_(k) is changed to “H” with an equivalent capacitor CP charged, arecovery current does not flow into the diodes D3 and D4 because theyare short-circuited. Furthermore, even if a parasitic transistor T3 ispresent in an NMOS transistor which implements the switch SW4, a currentI2 shown in FIG. 57 does not flow because a collector and an emitter areshort-circuited.

More specifically, if a power source to be supplied to the address drivecircuit AD2 is substantially removed, the generation of theshort-circuit current I2 can be avoided to prevent the breakdown of theIC. Therefore, an IC using a self-isolating technique can also beutilized. In other words, a reduction in a voltage is realized to widelychoose the IC. Therefore, a cost can be reduced.

It is necessary to transmit, at a high speed, a control signal CNT forcontrolling the switches SW3 and SW4, for example, drive datacorresponding to each address electrode A_(j). The drive data is givenfrom a predetermined control circuit. In the case where the voltage Va2is applied to the anode of the diode D4, it is necessary to protect thecontrol circuit.

Even if the control circuit and the voltage Va2 are isolated from eachother by a photocoupler in a conventional manner, no trouble is causedin respect of operation. In a high-speed address drive circuit having alarge number of signal lines, however, a high-speed photocoupler shouldbe used and furthermore, a large number of drive data segments arerequired. Therefore, a reduction in the cost is impeded very greatly.Therefore, the present invention has used a comparatively inexpensivecapacitor for isolation.

In this case, the charge and discharge of the capacitor for isolationinfluences a transfer delay of the drive data. For this reason, thepresent invention comprises a diode for rapidly performing the chargeand discharge of the capacitor. Moreover, the present invention alsoprovides a technique related to a sequence for discharging thecapacitor.

In order to relieve the transfer delay of the drive data, furthermore,the present invention also provides an isolation technique using a diodein place of the capacitor.

Differently from the conventional drive circuit SD3 shown in FIGS. 56and 57, the potential Va is applied to a scan electrode X through diodesD91 and D92 connected in antiparallel with each other in a drive circuitSD5 for a write discharge period. Consequently, even if an electricpotential tries to perform step-up by the equivalent capacitor providedin a display C_(jk), the electric potential of the scan electrode X isnot raised above the electric potential Va.

By the step-up using a capacitor C_(D), an electric potential (Vs+Vw) isapplied to the scan electrode X for a write preparation period as willbe described below. In addition, an electric potential Vs is applied forthe sustain discharge period.

Switches for applying the electric potentials Va, Vs and Vw to the scanelectrode X are constituted by MOS transistors. In order to protectthem, each of diodes D93 to D98 is provided in parallel with each of theswitches.

B. First Embodiment

FIG. 2 is a block diagram showing a first embodiment of the presentinvention. Two scan electrode groups XG and YG, each comprising aplurality of scan electrodes, and an address electrode group AGcomprising a plurality of address electrodes are provided in a surfacedischarge type plasma display panel CG having a plurality of displaycells arranged in a matrix.

FIG. 3 is an enlarged view showing a state obtained in the vicinity ofone display cell C_(jk) in the surface discharge type plasma displaypanel CG, in which one scan electrode X in the scan electrode group XGand one scan electrode Y_(k) are provided in parallel with each otherand an address electrode A_(j) is provided orthogonal to the scanelectrodes X and Y_(k) (Although a plurality of scan electrodes X areprovided, a common voltage is applied to all of them. Therefore, eachscan electrode X is not particularly distinguished for illustration).The display cell C_(jk) is formed on an intersecting point of theseelectrodes.

When scanning each of the scan electrodes X and Y_(k), datacorresponding to respective addresses are output from the addresselectrode A_(j) all at once to perform a write discharge. After anaddress period is terminated, the same signal is output to all theaddress electrodes for a sustain discharge period.

A plurality of push-pull type drive circuits for driving each addresselectrode A_(j) are provided and constitute an address drive circuit 22.Furthermore, a drive circuit for driving each scan electrode Y_(k) isprovided to constitute a scanning drive circuit DY. In addition, ascanning drive circuit DX for driving the scan electrode X is alsoprovided.

The scanning drive circuits DX and DY serve to drive the scan electrodesX and Y_(k) by a digital signal generating circuit 21, and furthermore,the address drive circuit 22 serves to drive the address electrode A_(j)through an isolation circuit 23 on receipt of a control signal and drivedata generated from a video signal VD.

A first common potential point 27 for applying an electric potential (afirst common potential: a ground potential in the present embodiment)which is a reference of the operation is connected to the digital signalgenerating circuit 21. A second common potential point 28 for applyingan electric potential (a second common potential) which is a referenceof the operation is connected to the address drive circuit 22.

Power control circuits 25, 24 and 26 are provided to generatepredetermined electric potentials W_HV and W_(—)5V (which are based onthe second common potential) and the second common potential on receiptof a first power control signal, a second power control signal and acommon potential control signal from the digital signal generatingcircuit 21, respectively.

(b-1) Digital Signal Generating Circuit

FIGS. 4 and 5 are circuit diagrams showing a connecting relationshipamong the digital signal generating circuit 21, the power controlcircuits 25, 24 and 26, the isolation circuit 23 and the address drivecircuit 22, which continue in a virtual line Q1—Q1. The digital signalgenerating circuit 21 sends, to the isolation circuit 23, an outputenable signal EN, a clock signal CLK and a data latch signal DL whichare control signals for controlling the address drive circuit 22 basedon the video signal VD received from the outside.

A power source necessary for the digital signal generating circuit 21 isobtained from the other terminal of a voltage source having one ofterminals to which the first common potential is applied (hereinafterreferred to as “a power source which is based on the first commonpotential”). In the drawing, the power source which is based on thefirst common potential is shown by an open circle. In the following, thepower source which is based on the first common potential will bereferred to as “a first 5V power source” if a voltage thereof is 5V, forexample. In the following, furthermore, a power source for applying anelectric potential Z is indicated as the same reference designation Z.

(b-2) Address Drive Circuit 22

The address drive circuit 22 is constituted by drive circuits 22 ₁ to 22_(n) having push-pull type input and output stages. For each of thedrive circuits 22 ₁ to 22 _(n), μPD 16327 manufactured by NEC can beemployed, for example. The second common potential point 28 is connectedto a common terminal of each of drive circuits 22 _(i) (i=1 to n). A 5Vpower source (a 5V power source which is shown by a solid circle in thedrawing and will be hereinafter referred to as “a second SV powersource”, and so are other voltages) based on a voltage source having aterminal to which the second common potential (hereinafter referred toas “a power source that is based on the second common potential”) isapplied is given to a power terminal VCC for an internal logic circuit,and an electric potential W_HV based on the second common potential isapplied to an HV power terminal. The electric potential W_HV isequivalent to the electric potential Va shown in FIG. 1.

Each of 64 output terminals of the drive circuits 22 _(i) to 22 _(n) isconnected corresponding to each of the address electrodes A_(j). Any onepiece of information about three colors (red, green and blue) istransmitted to one address electrode. Accordingly, (640×3/64=30) is aminimum value of the number n of the drive circuits in a VGA (VideoGraphics Array) specification, for example.

The control signals and the drive data which are transmitted through theisolation circuit 23 are input to an input terminal of each drivecircuit 22 _(i). Three kinds of control signals are input and 4-bitdrive data are input in parallel.

(b-3) Isolation Circuit 23

The isolation circuit 23 has a part 31 for transmitting the outputenable signal EN, and a part 32 for transmitting the clock signal CLK,the data latch signal DL and drive data. The isolation circuit 23 has afunction of outputting a signal obtained from the digital signalgenerating circuit 21 to the address drive circuit 22 while isolatingthe digital signal generating circuit 21 from a fluctuation in thesecond common potential. The control signals output from the isolationcircuit 23 are sent to all the drive circuits 22 _(i) and the drive datais transmitted to a data input of each of corresponding drive circuits22 _(i).

FIG. 6 is a circuit diagram showing a structure of the part 31. The part31 performs isolation by means of a photocoupler. The output enablesignal EN is sent to a driver G1. Electric potentials are applied fromthe first common potential point 27 and the first 5V power source to thedriver G1, respectively.

An output of the driver G1 is sent to a cathode of a diode D31. An anodeof the diode D31 is connected to that of an LED 100 of a photocouplerPC, and furthermore, is connected to the first 5V power source through apull-up resistor R1.

Since a buffer 101 of the photocoupler PC has an output terminal whichis an open collector, it is connected to the secondb 5V power sourcethrough a pull-up resistor R2. An output of the photocoupler PC issubjected to logical adjustment (waveform shaping and inversion) by alogic circuit G2. Common terminals of the photocoupler PC and the logiccircuit G2 are connected to the second common potential point 28, andrespective power terminals are connected to the second 5V power source.

When a signal “H” is input to the driver G1, the driver G1 outputs “H”.Since this signal reversibly biases the diode D31, a current does notflow to the diode D31. Consequently, a current I31 flows forward in theLED 100 through the pull-up resistor R1. Correspondingly, “L” is outputfrom the buffer 101 and “H” is output from the logic circuit G2 whichfunctions as an inverter.

When a signal “L” is input to the driver G1, the driver G1 outputs “L”.Since this signal forward biases the diode D31, a current I32 flows inthe diode D31 toward the driver G1. Consequently, a current does notflow to the LED 100, and the buffer 101 outputs a high-impedance state(“Z”). Then, “H” is input to the logic circuit G2 by the pull-upresistor R2, and the logic circuit G2 outputs “L”.

FIG. 7 is a circuit diagram showing a structure of a component 32 a ofthe part 32. In the part 32, the necessary number of components 32 a fortransmitting the clock signal CLK, the data latch signal DL and thedrive data are provided in parallel. This number will be specificallydescribed in an eighth embodiment.

In the component 32 a, for example, the data latch signal DL obtainedfrom the digital signal generating circuit 21 (so are the clock signalCLK and one bit of the drive data) is input to a buffer B1 (for which74HC244 or the like can be employed, for example), and an outputterminal of the buffer B1 is connected to one of terminals of acapacitor C3 and a cathode of a diode D32 in common. Operating power issupplied from the first common potential point 27 and the first 5V powersource to the buffer B1, respectively.

Furthermore, an anode of the diode D32 is connected to the first commonpotential point 27. The other terminal of the capacitor C3 is connectedto an input terminal of a buffer B2 (for which the 74HC244 or the likecan be employed, for example) and an anode of a diode D33 in common. Theelectric potential W_(—)5V is applied to a cathode of the diode D33together with a power terminal of the buffer B2. The second commonpotential point 28 is connected to a common terminal of the buffer B2.In other words, the operating power is supplied from the second commonpotential point 28 and the power source W_(—)5V to the buffer B1,respectively.

The operation of the component 32 a will be hereinafter described indetail in (b-7) in relation to other circuits.

(b-4) Power Control Circuit 24

FIG. 8 is a circuit diagram showing a structure of the power controlcircuit 24. The electric potential W_(—)5V output from the power controlcircuit 24 is based on the second common potential, and 5V is suppliedonly for a period in which the control signal and the drive data aretransmitted to the address drive circuit 22 and the second commonpotential is supplied for other periods, thereby preventing erroneoustransfer of the control signal and drive data.

A part 31 p is the same as the part 31 p shown in FIG. 6, that is, thecircuit constituted by the driver G1, the diode D31, the resistor R1,the photocoupler PC and the resistor R2.

The second power control signal sent from the digital signal generatingcircuit 21 is transmitted through the part 31 p and is input to thedriver G2. Both a PMOS transistor P1 on a high arm side and an NMOStransistor N1 on a low arm side are driven based on the output of thedriver G2.

More specifically, the output of the driver G2 is sent to a gate of theNMOS transistor N1 through a gate resistor R3 and a diode D34 which areconnected in parallel with each other. An anode of the diode D34 isconnected to the gate of the NMOS transistor N1. The NMOS transistor N1has a source connected to the second common potential point 28, and adrain connected to an output terminal of the power control circuit 24.

An output terminal of the driver G2 is connected to a gate of the PMOStransistor P1 through a capacitor C1. The second 5V power source isgiven to a source of the PMOS transistor P1, and a drain of the PMOStransistor P1 is connected to the output terminal of the power controlcircuit 24. Parallel connection of a resistor R4 and a Zener diode Z1 isprovided between the second 5V power source and the gate of the PMOStransistor P1. The Zener diode Z1 has an anode connected to the gate ofthe PMOS transistor P1.

The NMOS transistor N1 and the PMOS transistor P1 are provided withprotective diodes D22 and D21, respectively. They have a function ofcausing a current to flow in a reverse direction to a current whichusually flows to each transistor.

For the driver G2, it is necessary to employ an IC having an input TTLlevel and serving to output a power level to be given to itself. Forexample, TC4429 (manufactured by TelCom Co., Ltd.) or the like is used.A common terminal of the driver G2 is connected to the second commonterminal 28. A second 15V power source is supplied as a power source.

The PMOS transistor P1 and the NMOS transistor N1 are totem-poleconnected, and can output the electric potential W_(—)5V with a lowimpedance from their drains. A part 24 p enclosed by a one-dotted dashedline in the drawing functions as a drive circuit for the PMOS transistorP1 and the NMOS transistor N1.

In the case where the power control circuit 24 supplies the secondcommon potential as the electric potential W_(—)5V, a second powercontrol signal is set to “H”. In the same manner as the operation of thepart 31 of the isolation circuit 23, the driver G2 outputs “H”. Thedriver G2 operates based on a voltage supplied from the second commonpotential point 28 and the second 15V power source. Therefore, theoutput “H” from the driver G2 is about 15V for the second commonpotential. Consequently, the NMOS transistor N1 is turned on through thegate resistor R3. Thus, the electric potential W_(—)5V takes the secondcommon potential.

On the other hand, a source of the PMOS transistor P1 is connected tothe second 5V power source and the capacitor Cl holds a voltage of about5V. Accordingly, an electric potential of 20V is instantaneously appliedto the gate of the PMOS transistor P1 with respect to the second commonpotential so that the PMOS transistor P1 is turned off. At this time,the Zener diode Z1 is forward biased. Therefore, the gate potential ofthe PMOS transistor P1 shortly returns to 5V based on the second commonpotential.

In the case where 5V for the second common potential is to be suppliedas the electric potential W_(—)5V, the second power control signal isset to “L”. In the same manner as the operation of the part 31 of theisolation circuit 23, the driver G2 outputs “L”. The electric potentialis almost equal to the second common potential.

Since electric charges stored in the gate of the NMOS transistor N1 arerapidly discharged through the diode D34, the NMOS transistor N1 isturned off. Furthermore, the electric potential of one of terminals ofthe capacitor C1 on the side connected to the output terminal of thedriver G2 is reduced with a potential difference of about 15V.Accordingly, the gate potential of the PMOS transistor P1 becomes −10Vfor the second common potential so that the PMOS transistor P1 is turnedon. At this time, the Zener diode Z1 functions to avoid applying anovervoltage to the gate of the PMOS transistor P1, thereby protectingthe PMOS transistor P1.

The gate potential of the PMOS transistor P1 is gradually raised toward5V by a resistor R4. However, when the gate of the PMOS transistor P1reaches 0V, the PMOS transistor P1 is turned off. Therefore, it isnecessary to carefully set the values of the capacitor C1 and theresistor R4.

In the case where the second common potential is to be supplied as theelectric potential W_(—)5V, the NMOS transistor N1 is turned on with alittle delay for the output of the driver G2 by the gate resistor R3,while the PMOS transistor P1 is immediately turned off. Accordingly, itis possible to prevent a current from flowing between the PMOStransistor P1 and the NMOS transistor N1 (a short circuit between arms).Furthermore, in the case where 5V is supplied as the electric potentialW_(—)5V, the NMOS transistor N1 is rapidly turned off for the output ofthe driver G2 because it is bypassed by the diode D34. By suchoperation, it is possible to minimize the short circuit between the armswhich is caused by the delayed turn-off operation of the NMOS transistorN1.

(b-5) Power Control Circuit 25

FIG. 9 is a circuit diagram showing a structure of the power controlcircuit 25. An electric potential W_HV output from the power controlcircuit 25 is based on the second common potential, and 70V is suppliedonly for an address period and the second common potential is suppliedfor other periods, thereby protecting the output stage of the addressdrive circuit 22.

A pair of first power control signals (on H and L sides) which do notsimultaneously take “H” are transmitted to the power control circuit 25.The “H side” and the “L side” indicate that the high arm and low armsides of a transistor in the final stage of the power control circuit 25are controlled and do not indicate the level of the first power controlsignal.

The power control circuit 25 includes a pair of parts 31 correspondingto the pair of first power control signals, NMOS transistors N3 and N2which are totem-pole connected between a second 70V power source and thesecond common potential point 28 and a gate circuit 7 for a push-pulldriver for driving the NMOS transistors N3 and N2 on receipt ofrespective outputs of the pair of parts 31. A signal transmitted throughthe part 31 is sent to the push-pull drive circuit 7. Furthermore,protective diodes D24 and D23 are connected to the NMOS transistors N3and N2 in parallel.

The NMOS transistor N3 on the low arm side has a source connected to thesecond common potential point 28 and a drain connected to the second 70Vpower source. A source of the NMOS transistor N2 is connected to a drainof the NMOS transistor N3 on the low arm side in common, to which theelectric potential W_HV is output.

The second common potential, the second 5V power source and the second15V power source are supplied to the push-pull drive circuit 7. Astructure of the push-pull drive circuit 7 will be described below indetail.

The H and L sides of the first power control signal are transmittedthrough the parts 31, respectively. The outputs of the parts 31 functionas high and low arm side inputs of the gate circuit 7 for a push-pulldriver. The gate circuit 7 for a push-pull driver sends a drive signalto respective gates of the NMOS transistors N2 and N3.

By setting values on the H and L sides of the first power control signalto “H” and “L” respectively, the gate circuit 7 for a push-pull driverturns off the NMOS transistor N3 and the NMOS transistor N2 is turned onto supply, as the electric potential W_HV, 70V which is based on thesecond common potential. Conversely, by setting the values on the H andL sides of the first power control signal to “L” and “H”, the gatecircuit 7 for a push-pull driver turns on the NMOS transistor N3 andturns off the NMOS transistor N2 to supply the second common potentialas the electric potential W_HV.

(b-6) Power Control Circuit 26

FIG. 10 is a circuit diagram showing a structure of the power controlcircuit 26. The second common potential output from the power controlcircuit 26 takes the first common potential or an electric potential(hereinafter referred to as “a first HV potential”) which is higher thanthe first common potential by a predetermined voltage HV (>W_HV) basedon the second common control signal sent from the digital signalgenerating circuit 21. The first HV potential is equivalent to theelectric potential Va2 shown in FIG. 1.

A pair of common potential control signals (on H and L sides) which donot simultaneously take “H” are sent to the power control circuit 26.The “H side” and the “L side” indicate that the high and low arm sidesof a transistor in the final stage of the power control circuit 26 arecontrolled and do not indicate the level of the common control signal.

The power control circuit 26 comprises a push-pull drive circuit 7 forreceiving the common potential control signal, and NMOS transistors N4and N5 which are totem-pole connected between the first HV power sourceand the first common potential point 27. Furthermore, protective diodesD26 and D25 are provided on the NMOS transistors N4 and N5,respectively.

The NMOS transistor N5 on the low arm side has a source connected to thefirst common potential point 27, and the NMOS transistor N4 on the higharm side has a drain connected to the first HV power source through aresistor R5. A pair of outputs of the gate circuit 7 for a push-pulldriver are given to the respective gates.

A source of the NMOS transistor N4 is connected to the drain of the NMOStransistor N5 in common, to which the second common potential is output.

Differently from the power control circuit 25, the first commonpotential, the first 5V power source and the first 15V power source aresupplied to the push-pull drive circuit 7.

In the case where the first HV potential is to be supplied as the secondcommon potential, the values on the H and L sides of the commonpotential control signal are set to “H” and “L”, respectively. The gatecircuit 7 for a push-pull driver turns off the NMOS transistor N5 andturns on the NMOS transistor N4. Accordingly, the electric potentialsupplied from the second common potential point 28 (that is, the secondcommon potential) by the first HV power source and the resistor R5 isgradually raised to the first HV potential.

On the other hand, in the case where the first common potential (groundpotential) is to be output to the second common potential point 28, thevalues on the H and L sides of the common potential control signal areset to “L” and “H”, respectively. The gate circuit 7 for a push-pulldriver turns on the NMOS transistor N5 and turns off the NMOS transistorN4. Consequently, the second common potential point 28 immediatelysupplies the first common potential.

(b-7) Gate Circuit 7 for Push-pull Driver

FIG. 11 is a circuit diagram showing a structure of the gate circuit 7for a push-pull driver and a switch circuit 70 connected thereto. Theswitch circuit 70 includes two NMOS transistors N6 and N7 which aretotem-pole connected, and the gate circuit 7 for a push-pull driverdrives these NMOS transistors.

A source of the NMOS transistor N7 on a low arm side is connected to acommon potential point 30, and a drain of the NMOS transistor N6 on ahigh arm side is connected to a high electric potential point 292 whichis based on the common potential point 30. In FIG. 11, an electricpotential point or a power source which is based on the common potentialpoint 30 is shown by a square. A drain of the NMOS transistor N7 isconnected to a source of the NMOS transistor N6 in common, from which anoutput is obtained.

The gate circuit 7 for a push-pull driver includes a gate driving IC 75(IR2113S manufactured by IR Co., Ltd., for example). Common terminals VSand COM on high and low arm sides of the gate driving IC 75 areconnected to the sources of the NMOS transistors N6 and N7,respectively. As a result, the common potential point 30 is connected tothe common terminal COM on the low arm side in the same manner as theswitch circuit 70.

Gate output terminals HO and LO on the high and low arm sides areconnected to gates of the NMOS transistors N6 and N7 through elementparallel connections, respectively. The element parallel connection is aparallel connection of a diode Dg and a gate resistor Rg. An anode ofthe diode Dg is connected close to the NMOS transistors N6 and N7. Theelement parallel connection is provided to turn off the NMOS transistorsN6 and N7 at a high speed and to prevent a short circuit between arms.

The gate driving IC 75 includes a common terminal VSS for a logic as apower common terminal as well as a common terminal VS on the high armside and a common terminal COM on the low arm side. The common terminalVSS for a logic is also connected to the common potential point 30 inthe same manner as in the switch circuit 70.

The gate driving IC 75 includes a power input terminal VDD for a logic,a power input terminal VB for a gate signal on the high arm side and apower input terminal VCC for a gate signal on the low arm side as powerinput terminals. Voltages of 5V and 15V based on the electric potentialof the common potential point 30 are applied to the power input terminalVDD for a logic and the power input terminal VCC for a gate signal onthe low arm side, respectively. A 15V power source which is based on thecommon terminal VS on the high arm side is required for the power inputterminal VB for a gate signal on the high arm side. Therefore, a voltageof 15V is applied through a diode D70. A capacitor Cb is providedbetween the power input terminal VCC for a gate signal on the low armside and the common terminal COM on the low arm side and between thepower input terminal VB for a gate signal on the high arm side and thecommon terminal VS on the high arm side, respectively.

A high arm side control input and a low arm side control input are givento the gate circuit 7 for a push-pull driver. These are input to controlinput terminals HIN and LIN on the high and low arm sides of the driverIC 75. In the case where the high arm side control input has “H”, a gatesignal having the “H” based on the common terminal VS on the high armside is output to the gate of the NMOS transistor N6 on the high armside through the gate resistor Rg. The turn-on operation of the NMOStransistor N6 is delayed for the gate signal according to a dischargetime constant determined by an input capacity of itself and the gateresistor Rg. Furthermore, if the source potential of the NMOS transistorN6 is raised more, the electric potential of the common terminal VS onthe high arm side becomes higher.

In the case where the high arm side control input has “L”, the gatesignal for the gate of the NMOS transistor N6 has “L”. Since the diodeDg is forward biased, electric charges are extracted from the gate ofthe NMOS transistor N6 at a high speed irrespective of the dischargetime constant. As a result, the NMOS transistor N6 is rapidly turned offfor the gate signal.

The operation of the low arm side control input and the NMOS transistorN7 is the same as described above. The same common potential (that is,an electric potential to be applied by the common potential point 30) asthe common potential on which the high arm side control input and thelow arm side control input are based should be applied to the source ofthe NMOS transistor N7.

In this circuit, while the turn-on of the NMOS transistors N6 and N7 isdelayed according to the discharge time constant by the existence of theresistor Rg, the turn-off thereof is instantaneously performed becausebypassing is carried out by the diode Dg. By such operation, even if thehigh arm side control input and the low arm side control input arechanged at the same time, it is possible to prevent a short circuitbetween arms from being caused by the delay of the turn-off of thetransistor.

Of course, the high arm side control input and the low arm side controlinput should not be set to “H” at the same time in order to avoid theshort circuit between the arms.

In the case where the gate circuit 7 for a push-pull driver is used inthe power control circuit 25, the common potential point 30 correspondsto the second common potential point 28 and the NMOS transistors N6 andN7 correspond to the NMOS transistors N2 and N3, respectively.Furthermore, the H and L sides of the first power control signalcorrespond to the high arm side control input and the low arm sidecontrol input, respectively.

On the other hand, in the case where the gate circuit 7 for a push-pulldriver is used in the power control circuit 26, the common potentialpoint 30 corresponds to the first common potential point 27 and the NMOStransistors N6 and N7 correspond to the NMOS transistors N4 and N5,respectively. Furthermore, the H and L sides of the common potentialcontrol signal correspond to the high arm side control input and the lowarm side control input, respectively.

(b-8) Explanation of Operation according to the Present Embodiment

FIG. 12 is a timing chart showing operation according to the presentembodiment. The operation according to the present embodiment is broadlydivided into four stages;

(I) Write preparation (priming),

(II) Write discharge,

(III) Electric charge erasing (reset), and

(IV) Sustain discharge.

The respective stages will be described below in order.

(I) Write Preparation (Priming)

In this sequence, an erase pulse is input to erase electric chargesstored in each display cell C_(jk) and space charges are caused toremain as a priming for a write discharge to be carried out next,thereby performing the preparation for the write discharge in thesurface discharge type plasma display panel.

In the write preparation, the control signal and the drive data whichare transmitted from the digital signal generating circuit 21 are set toan inactive state. More specifically, the drive data, the clock signalCLK and the data latch signal are forcedly set to “L” and the outputenable signal EN is forcedly set to “H”. Such setting is performed bythe digital signal generating circuit 21.

The H side of the first power control signal has “L”. In general, the Lside of the first power control signal has a logic different from thaton the H side. Consequently, the electric potential W_HV takes thesecond common potential. The second power control signal has “L”.Consequently, the electric potential W_(—)5V takes the second commonpotential.

At a time t1, the H side of the common potential control signal ischanged from “L” to “H” (the L side of the common potential controlsignal generally has a logic different from that on the H side), and anelectric potential HV based on the first common potential (groundpotential) is supplied from the second common potential point 28. At thetime t1, furthermore, the scan electrode X has an electric potentialwhich is raised from a ground potential 0V to an electric potential Vp.The electric potentials Vp and HV are selected such that a greaterdischarge than the sustain discharge can be performed in the displaycell C_(jk). For example, the electric potential Vp is set to the sum ofelectric potentials Vw and Vs shown in FIG. 1, and the electricpotential HV is set to the electric potential Va2.

FIG. 13 is a circuit diagram showing a connecting relationship among apartial equivalent circuit of the drive circuit 22 _(i), a component 32a provided in the isolation circuit 23 for sending an input signalcorresponding to an output stage for one bit of the drive circuit 22_(i), and the power control circuits 24, 25 and 26. A part 25 p of thepower control circuit 25 indicates the gate circuit 7 for a push-pulldriver and a pair of parts 31 collectively. FIG. 13 illustrates acurrent flow obtained when the electric potential HV based on the firstcommon potential is supplied from the second common potential point 28.

It is apparent from a contrast between FIGS. 13 and 1 that the powercontrol circuits 26 and 25 correspond to the circuits DR0 and DR1,respectively. In more detail, transistors N2, N3, N4 and N5 correspondto the switches SW12, SW13, SW10 and SW11 respectively and protectivediodes D23, D24, D25 and D26 correspond to the diodes D12, D13, D11 andD10 respectively.

The output stage for one bit of the drive circuit 22 _(i) is constitutedby NMOS transistors N9 and N10 for turning on/off according to thecontrol of a control circuit provided in the drive circuit 22 _(i) andprotective diodes D45 and D46 provided in parallel therewith. Aninternal circuit operates on receipt of the electric potential 5V andthe electric potential W_HV which are based on the second commonpotential. The output stage for one bit of the drive circuit 22 _(i)corresponds to the address drive circuit AD2 shown in FIG. 1, the NMOStransistors N9 and N10 correspond to the switches SW3 and SW4, and theprotective diodes D45 and D46 correspond to the diodes D3 and D4,respectively.

The electric potential W_HV to be given to the address electrode isapplied to a drain of the NMOS transistor N9 for a write dischargeperiod, and a source of the NMOS transistor N9 is connected to anaddress electrode A_(j) through an output terminal of the drive circuit22 _(j). The NMOS transistor N10 has a source to which the second commonpotential point 28 is connected, and a drain connected to the addresselectrode A_(j) through the output terminal of the drive circuit 22_(i). The protective diodes D45 and D46 are connected in parallel withthe NMOS transistors N9 and N10 respectively, and have a function ofcausing a current to flow in a reverse direction to a current whichusually flows to the NMOS transistors N9 and N10.

Each of the buffers B1 and B2 usually includes respective two sets ofPMOS and NMOS transistors (high and low arm sides) for input and outputstages which are totem-pole connected. Protective diodes are provided onthe high and low arm sides in the input and output stages, respectively.For example, the output stage of the buffer B1 is constituted by a PMOStransistor P2 and an NMOS transistor N8 which are totem-pole connected,and protective diodes D41 and D42 are provided in the PMOS transistor P2and the NMOS transistor N8, respectively. Furthermore, the input stageof the buffer B2 is constituted by a PMOS transistor P3 and an NMOStransistor N1 which are totempole connected, and protective diodes D43and D44 are provided in the PMOS transistor P3 and the NMOS transistorN1, respectively.

The H and L sides of the first power control signal have “L” and “H”,respectively. Therefore, the NMOS transistors N3 and N2 of the powercontrol circuit 25 are on and off, respectively. Furthermore, the secondpower control signal has “L”. Therefore, the PMOS transistor P1 of thepower control circuit 24 is off and the NMOS transistor N1 thereof ison.

Since the drive data is forcedly set to “L”, the PMOS transistor P2 isoff and the NMOS transistor N8 is on. Furthermore, the NMOS transistorsN9 and N10 of the drive circuit 22i are off and on respectively by thecontrol of the control circuit provided in the drive circuit 22 _(i)based on the fact that the output enable signal EN is set to “H”.

At the time t1, the H and L sides of the common potential control signalare changed to “H” and “L”, respectively. In the power control circuit26, therefore, the NMOS transistors N4 and N5 are turned on and off,respectively. Accordingly, a current I91 flows from the first HV powersource to the second common potential point 28 through the resistor R5and the NMOS transistor N4. A part of the current I91 becomes a currentI92 which flows from the second common potential point 28 to the drivecircuit 22 _(i) and then to the address electrode A_(j) through theprotective diode D46. Consequently, electric charges are stored in thedisplay cell C_(jk).

A part of the current I91 becomes a current I93 which transiently flowsto the first common potential point 27 through the protective diode D44of the buffer B2, the capacitor C3 and the NMOS transistor N8 of thebuffer B1. In other words, the capacitor C3 is charged such that theside connected to an input terminal of the buffer B2 has a high electricpotential.

Thus, a charging current flows to the capacitor C3. If a capacitance ofthe capacitor C3 is set small, for example, to about 470 pF, a periodfor which the current flows can be more reduced than a period for whicha voltage of the address electrode should be raised. Accordingly, thecomponent 32 a is substantially isolated from a fluctuation in thesecond common potential. Consequently, the digital signal generatingcircuit 21 is also isolated from the fluctuation in the second commonpotential.

Furthermore, the resistor R5 is provided in the power control circuit 26to set a maximum value of the current I93 so as not to exceed theprotection capability of the protective diode D44 and the transistor N8in which a rating is set corresponding to the output capability of thebuffer B1.

At a time t2, next, the H side of the common potential control signal isset to “L” and the first common potential is supplied from the secondcommon potential point 28. Furthermore, the electric potential of thescan electrode X is set to a ground potential Consequently, a self-erasedischarge is performed in the display cell C_(jk) so that space chargesacting as a priming remain.

FIG. 14 corresponds to FIG. 13, and is a circuit diagram showing acurrent flow obtained when the first common potential is supplied fromthe second common potential point 28. Also at the time t2, the firstpower control signal, the second power control signal, the drive dataand the control signal are not changed. Therefore, the on/off states ofthe transistors N1, P1, N3, N2, N9, N10, P2 and N8 are not changed.

However, the NMOS transistors N4 and N5 are turned off and on in thepower control circuit 26, respectively. Therefore, the first commonpotential is supplied to the second common potential point 28.Accordingly, the electric charges stored in the display cell C_(jk) flowas a current I94 from the address electrode A_(j) to the second commonpotential point 28 through the protective diode D45 of the drive circuit22 _(i) and the NMOS transistor N3 of the power control circuit 25. Onthe other hand, a current I95 also flows from the address electrodeA_(j) to the second common potential point 28 through the NMOStransistor N10. These currents I94 and I95 flow from the second commonpotential point 28 to the first common potential point 27 through theNMOS transistor N5 of the power control circuit 26 so that the electriccharges stored in the display cell C_(jk) are discharged.

On the other hand, the capacitor C3 charged between the times t1 and t2discharges the stored electric charges. Based on the discharge, acurrent I96 flows to the second common potential point 28 through theprotective diode D43 of the buffer B2, the diode D33 and the NMOStransistor N1 of the power control circuit 24. The current I96 flowsfrom the second common potential point 28 to the first common potentialpoint 27 through the NMOS transistor N5 of the power control circuit 26.Furthermore, the current I96 flows from the first common potential point27 to the capacitor C3 through the protective diode D42 of the buffer B1and the diode D32.

The diodes D32 and D33 can quickly discharge the capacitor C3, and canrapidly reduce the electric potential of the second common potentialpoint 28 down to the first common potential (an electric potential equalto or less than 500 nsec.) Furthermore, the diodes D32 and D33 help thefunctions of the protective diodes D42 and D43. Therefore, the component32 a is substantially isolated from the fluctuation in the second commonpotential.

As described above, the electric potential of the second commonpotential point 28 is varied between the first common potential and theelectric potential of the first HV power source. Consequently, apulse-shaped voltage HV can be generated on the address electrode A_(j)correspondingly.

(II) Write discharge

In this sequence, the voltage Va (<HV) is applied to all the addresselectrodes A_(j) at once corresponding to respective data to perform awrite discharge at the time of each line scanning.

For a write discharge period, the H and L sides of the common potentialcontrol signal keep “L” and “H” respectively, and the NMOS transistorsN4 and N5 are off and on in the power control circuit 26 respectively.Accordingly, the second common potential is set to the first commonpotential.

At a time t3, the H and L sides of the first power control signal arechanged to “H” and “L” respectively, and the second power control signalis also changed to “H”. Consequently, the PMOS and NMOS transistors P1and N1 of the power control circuit 24 are turned on and offrespectively, and the NMOS transistors N2 and N3 of the power controlcircuit 25 are turned on and off respectively. Since the second commonpotential is equal to the first common potential, the electricpotentials W_(—)5V and W_HV have values of 5V and 70V based on the firstcommon potential respectively. Thus, each electric potential is set.Therefore, the drive data can be transferred in a write dischargesequence which has conventionally been performed, thereby performingwrite from the address electrode. For example, the scan electrode Y_(k)is varied between a scan potential −V_(sc) and an electric potential −Vswhich are negative.

For the write discharge period, the control signal and the drive datawhich are transmitted from the digital signal generating circuit 21 arenot forcedly set to an inactive state but are changed between “H” and“L”. There will be described the charge/discharge of the capacitor C3which is performed when the clock signal CLK, the data latch signal DLand the drive data to be processed in the part 32 are changed between“H” and “L”.

FIG. 15 is a circuit diagram showing a connecting relationship betweenthe power control circuit 26 and the component 32 a. FIG. 15 illustratesa current flow obtained when the data latch signal DL sent from thedigital signal generating circuit 21 is changed from “L” to “H” (so arethe clock signal CLK and one bit of the drive data), for example.

When the data latch signal DL is changed from “L” to “H”, the PMOStransistor P2 and the NMOS transistor N8 in the output stage of thebuffer B1 are turned on and off, respectively. Consequently, an electricpotential of an output terminal of the buffer B1 is suddenly raised from0V to 5V. Therefore, this fluctuation is transmitted to the buffer B2through the capacitor C3, and rapidly turns on and off the NMOStransistor N11 and the PMOS transistor P3 in an input stage of thebuffer B2, respectively. Consequently, the NMOS transistor on the lowarm side and the PMOS transistor on the high arm side in an output stageof the buffer B2 are turned off and on respectively, and an output ofthe buffer B2 is changed from “L” to “H”.

Thus, the step-up of a voltage can be implemented by using the capacitorC3. Therefore, a transition of the data latch signal DL can be rapidlytransmitted in the component 32 a.

When the data latch signal DL is “L”, the PMOS transistor P3 of thebuffer B2 is turned on. Therefore, more electric charges than in aterminal E1 on the side of the capacitor C3 connected to the buffer B1are stored in a terminal E2 on the side connected to the buffer B2. Morespecifically, such a voltage as to raise an electric potential on thebuffer B2 side more than on the buffer B1 side is kept by the capacitorC3. In this case, a current flows to the protective diode D21 of thepower control circuit 24 through the diode D33 in addition to theprotective diode D43 which is usually provided on the high arm side ofthe buffer B2. By such operation, an unnecessary increase in a voltageis not caused in the input stage of the buffer B2. In other words, theprotective diode D21 of the power control circuit 24 also protects theinput stage of the buffer B2.

Then, the capacitor C3 is charged in a reverse direction by a microleakage current I103 of the NMOS transistor N11 of the buffer B2 and acurrent I101 flowing in the PMOS transistor P2 of the buffer B1 so thatan electric potential on the terminal E1 is more raised than that on theterminal E2.

FIG. 16 is a circuit diagram corresponding to FIG. 15, illustrating acurrent flowing when the data latch signal DL is changed from “H” to“L”. The PMOS and NMOS transistors P2 and N8 provided in the outputstage of the buffer B1 are turned off and on, respectively.Consequently, the electric potential on the output terminal of thebuffer B1 is suddenly reduced from 5V to 0V. Therefore, this fluctuationis transmitted to the buffer B2 through the capacitor C3, and rapidlyturns off and on the NMOS and PMOS transistors N11 and P3 of the bufferB2, respectively. Consequently, the NMOS transistor on the low arm sideand the PMOS transistor on the high arm side in the output stage of thebuffer B2 are turned on and off respectively, and the output of thebuffer B2 is changed from “H” to “L”.

When the data latch signal DL is “H”, the electric potential on theterminal E1 of the capacitor C3 is higher than that on the terminal E2.However, since the NMOS transistor N8 on the low arm side in the outputstage of the buffer B1 is turned on, electric charges stored in theterminal E1 of the capacitor C3 become a current I104 to flow to thefirst common potential point 27. Furthermore, the current I104 reachesthe terminal E2 of the capacitor C3 through the protective diode D25 ofthe power control circuit 26 and the protective diode D44 of the bufferB2. Consequently, the capacitor C3 is discharged.

However, the capacitor C3 further starts to be charged in a reversedirection. The reason is that the electric charges are supplied from thesecond 5V power source to the terminal E2 of the capacitor C3 by a microleakage current I106 of the PMOS transistor P3 of the buffer B2 becausethe PMOS transistor P1 of the power control circuit 24 is on.

(III) Electric Charge Erasing

After respective drive data are written to all the address electrodes bythe write discharge, an electric charge erasing sequence is performed.

The H and L sides of the common potential control signal keep “L” and“H” respectively, and the second common potential keeps the first commonpotential.

At a time t4, the H and L sides of the first power control signal arechanged to “L” and “H” respectively, and the second power control signalis also changed to “L”. Consequently, the PMOS and NMOS transistors P1and N1 of the power control circuit 24 are turned off and onrespectively, and the NMOS transistors N2 and N3 of the power controlcircuit 25 are turned off and on respectively. The electric potentialsW_(—)5V and W_HV become equal to the second common potentialrespectively. However, since the second common potential is equal to thefirst common potential, the electric potentials W_(—)5V and W_HV finallybecome equal to the first common potential.

At the time t4, the output enable signal EN has already been set to “H”(inactive). Furthermore, the drive data, the clock signal CLK and thedata latch signal DL are forcedly set to “L” to become inactive at thetime t4. Moreover, the electric potential of the scan electrode Y_(k) isset to 0V.

Thus, the electric charges of the charged capacitor C3 can be dischargedby the write discharge. In this case, the electric potential W13 HV is0V. Therefore, no voltage is applied to both terminals of a seriesconnection of the transistors N9 and N10 in the output stage of thedrive circuit 22 _(i) so that the address electrode A_(j) is notaffected.

FIG. 17 is a circuit diagram showing a connecting relationship betweenthe power control circuit 26 and the component 32 a. FIG. 17 illustratesa discharge of the capacitor C3 when the electric potential on theterminal E1 of the capacitor C3 has been higher than that on theterminal E2.

Since the second power control signal has “L”, the PMOS and NMOStransistors P1 and N1 of the power control circuit 24 are off and onrespectively. Since the drive data, the clock signal CLK and the datalatch signal are “L”, the PMOS and NMOS transistors P2 and N8 of thebuffer B1 are off and on respectively. Since the H and L sides of thecommon potential control signal keep “L” and “H” respectively, the NMOStransistors N4 and N5 are off and on in the power control circuit 26respectively.

The electric charges stored in the capacitor C3 are discharged throughthe NMOS transistor N8, the first common potential point 27, theprotective diode D25 of the power control circuit 26, the second commonpotential point 28 and the protective diode D44 of the buffer B2 in thisorder in the same manner as the current I104 shown in FIG. 16.

The current I106 shown in FIG. 16 does not flow. The reason is that thePMOS transistor P1 of the power control circuit 24 is off.

FIG. 18 is a circuit diagram showing a connecting relationship betweenthe power control circuit 26 and the component 32 a. FIG. 18 illustratesa discharge of the capacitor C3 when the electric potential on theterminal E2 of the capacitor C3 has been higher than that on theterminal E1.

The electric charges stored in the capacitor C3 are discharged throughthe protective diode D43 of the buffer B2, the diode D33, the NMOStransistor N1 of the power control circuit 24, the second commonpotential point 28, the NMOS transistor N5 on the low arm side of thepower control circuit 26, the first common potential point 27, theprotective diode D42 of the buffer B1 and the diode D32 in this order.

The requirements for the discharge are met for the priming dischargesequence period and a sustain discharge sequence period which will bedescribed below as well as the above-mentioned timing. Therefore, thecapacitor C3 is discharged.

(IV) Sustain discharge

After the electric charge erasing period is terminated, a sustaindischarge for light emission between the scan electrodes X and Y_(k) iscarried out.

Also at a time t5, the output enable signal EN is inactive with “H” andthe drive data, the clock signal CLK and the data latch signal DL areinactive with “L”. The “H” side of the first power control signal andthe second power control signal have “L” successively to the time t4,and the electric potentials W_(—)5V and W_HV take the second commonpotential.

However, the common potential control signal is changed from “L” to “H”at the time t5. Therefore, the second common potential becomes equal toan electric potential supplied from the first HV power source. In otherwords, a voltage HV is applied to the address electrode A_(j). When asustain discharge period is terminated at a time t6, the H side of thecommon potential control signal is changed from “H” to “L” so that thesecond common potential takes the first common potential (groundpotential). By such a fluctuation in the second common potential, astate of a current flowing among the address electrode A_(j), thecomponent 32 a and the power control circuits 24, 25 and 26 is the sameas that of the current described in (I) write preparation.

C. Second Embodiment

A second embodiment will describe a technique in which the component 32a shown in the first embodiment is deformed. FIG. 19 is a circuitdiagram showing a structure of a component 32 b. The component 32 a isreplaced by the component 32 b to constitute the part 32 of theisolation circuit 23.

The component 32 b is different only in that the second 5V potential isapplied to the buffer B2 to which the electric potential W_(—)5V isapplied in the component 32 a. More specifically, although an electricpotential is supplied to the diode D33 in the same manner as in thefirst embodiment, the second 5V potential is always applied to thebuffer B2. Accordingly, it is possible to relieve an output load of thepower control circuit 24 for applying the electric potential W_(—)5V toboth the diode D33 and the buffer B2.

An operating sequence according to the second embodiment is the same asthe operating sequence according to the first embodiment shown in FIG.12. Differences will chiefly be described below. FIG. 20 corresponds toFIG. 13 showing the first embodiment, and illustrates a current flowobtained when the electric potential HV based on the first commonpotential is supplied from the second common potential point 28. Thecurrent flow makes no difference between FIGS. 13 and 20.

FIG. 21 corresponds to FIG. 14 illustrating the first embodiment, and isa circuit diagram showing a current flow obtained when the first commonpotential is supplied from the second common potential point 28.Differently from the first embodiment, the second 5V power source isconnected to the high arm side of the buffer B2. Therefore, a currentI96 flows to an NMOS transistor N1 of the power control circuit 24through only the diode D33 without passing through the protective diodeD43 of the buffer B2.

FIG. 22 corresponds to FIG. 15 illustrating the first embodiment, and isa circuit diagram showing a current flow obtained when the data latchsignal DL is changed from “L” to “H”, for example. For a write dischargeperiod, the electric potential W_(—)5V takes the second 5V potential.Therefore, the flow of a current I102 has no substantial difference. Thecurrent flowing in the protective diode D43 is different only in that itflows to the second 5V power source without passing through the diodeD21.

FIG. 23 corresponds to FIG. 16 illustrating the first embodiment, and isa circuit diagram showing a current flow obtained when the data latchsignal DL is changed from “H” to “L”. The flow of the leakage currentI106 has no substantial difference. The leakage current I106 isdifferent only in that it is supplied from the second 5V power sourcewithout passing through the PMOS transistor P1 of the power controlcircuit 24.

FIG. 24 corresponds to FIG. 17 illustrating the first embodiment, and isa circuit diagram showing a discharge of the capacitor C3 when anelectric potential on the terminal E1 of the capacitor C3 has beenhigher than that on the terminal E2. The current flow makes nodifference between FIGS. 17 and 24.

FIG. 25 corresponds to FIG. 18 illustrating the first embodiment, and isa circuit diagram showing a discharge of the capacitor C3 when theelectric potential on the terminal E2 of the capacitor C3 has beenhigher than that on the terminal E1. Differently from the firstembodiment, the second 5V power source is connected to the high arm sideof the buffer B2 so that a discharge path does not include theprotective diode D43 of the buffer B2.

D. Third Embodiment

A third embodiment will describe a technique in which the component 32 ashown in the first embodiment is deformed. FIG. 26 is a circuit diagramshowing a structure of a component 32 c. The component 32 a is replacedby the component 32 c to constitute the part 32 of the isolation circuit23.

The component 32 c has a structure in which diodes D35 and D36 are addedto the component 32 a. The first 5V power source and the cathode of adiode D32 are connected to a cathode of the diode D35 and an anodethereof, respectively. Furthermore, the anode of the diode D33 and thesecond electric potential point 28 are connected to a cathode of thediode D36 and an anode thereof, respectively.

Thus, the diodes D35 and D36 are added so that an output of the bufferB1 can be set to “H” to rapidly cause the second common potential torise into the first HV potential in a sequence for the priming dischargesequence and the sequence for causing the sustain discharge as will bedescribed below.

FIG. 27 is a timing chart showing operation according to the presentembodiment. As compared with FIG. 12 which is a timing chartillustrating the first embodiment, a difference is made in that drivedata, the clock signal CLK, the data latch signal DL and the outputenable signal EN are forcedly set to “H” for a write preparation periodand a sustain discharge period. Before the write discharge period isstarted at a time t3, the drive data, the clock signal CLK and the datalatch signal DL are forcedly set to “L” at a time t6 and the outputenable signal is kept at “H”. The write preparation period is terminatedat the time t6, and the times t6 to t3 make a first electric chargeerasing period. For the write discharge period, the clock signal CLK,the data latch signal DL and the output enable signal EN are notforcedly set, respectively.

The electric charge erasing period set at the times t4 to t5 in thefirst embodiment is set as a second electric charge erasing period inthe present embodiment. At a time t7 for this period, the drive data,the clock signal CLK, the data latch signal DL and the output enablesignal EN are forcedly set to “H” again.

The operation according to the present embodiment will be describedbelow by attaching importance to differences made between the firstembodiment and the present embodiment. FIG. 28 is a circuit diagramcorresponding to FIG. 13 illustrating the first embodiment and shows acurrent flow obtained when the electric potential HV based on a firstcommon potential is supplied from the second common potential point 28.

Since a control signal, for example, the data latch signal DL isforcedly set to “H”, transistors P2 and N8 of the buffer B1 are on andoff, respectively. Furthermore, since the output enable signal EN isforcedly set to “H”, transistors N9 and N10 of the drive circuit 22 _(i)are off and on, respectively. In such a situation, when H and L sides ofthe common control signal have “H” and “L”at a time t1, NMOS transistorsN4 and N5 of the power control circuit 26 are turned on and offrespectively and a current I81 flows from the first HV power source tothe second common potential point 28 through the NMOS transistor N4. Apart of the current I81 flows from the second common potential point 28to the address electrode A_(j) through the protective diode D46 of thedrive circuit 22 _(i) in the same manner as the current I92 in the firstembodiment.

On the other hand, a part of the current I81 transiently flows as acurrent I83 from the second common potential point 28 through the diodesD36 and D44, a capacitor C3 and the diodes D35 and D41 in this order,thereby charging the capacitor C3. At this time, a voltage charged tothe capacitor C3 by the current I83 is almost equal to a differencebetween the electric potential of the first HV power source and 5V. Ascompared with the first embodiment in which the voltage charged to thecapacitor C3 is almost equal to the electric potential of the first HVpower source, it is apparent that a time required for charging is morereduced in the present embodiment than in the first embodiment. In otherwords, the electric potential of the second common potential point 28rapidly rises.

Furthermore, the diodes D35 and D36 are provided in parallel with theprotective diodes D41 and D44, respectively. Therefore, an impedance ofa charging path is lowered to help the above-mentioned operation beperformed more rapidly. Of course, as long as the protective diodes D41and D44 are provided in the buffers B1 and B2 respectively, thecomponent 32 a which does not include the diodes D35 and D36 can alsoexecute an operating sequence for the first electric charge erasingperiod shown in FIG. 27, thereby causing the electric potential of thesecond common potential point 28 to rise rapidly.

FIG. 29 corresponds to FIG. 14, and is a circuit diagram showing acurrent flow obtained when the first common potential is supplied fromthe second common potential point 28. In the same manner as in the firstembodiment, currents I94, I95 and I96 flow so that electric charges ofthe capacitor C3 are discharged. In the present embodiment, however, thecapacitor C3 is kept somewhat charged. Since “H” is input to the bufferB1, the PMOS transistor P2 thereof is turned on, electric charges aresupplied from the first 5V power source and an electric potential on theterminal E1 is higher than that on the terminal E2 by 5V. In order toperform a discharge, the first electric charge erasing period isprovided at the times t6 to t3.

FIG. 30 is a circuit diagram showing the discharge of the capacitor C3for the first electric charge erasing period. Since the drive data, thedata latch signal DL and the clock signal CLK are forcedly set to “L”,almost the same operation as for the electric charge erasing periodaccording to the first embodiment shown in FIG. 17 is performed. Thediode D36 is connected in the same direction in parallel with theprotective diode D44 of the buffer B2. Therefore, a difference is madeonly in that the diode D36 is added to a discharging current path inparallel with the protective diode D44.

Although the operation to be performed for the write discharge period isalmost the same as in the first embodiment, a path for a current forcharging and discharging the capacitor C3 is somewhat different when alevel input to the buffer B1 is changed. FIG. 31 is a circuit diagramcorresponding to FIG. 15 and shows a current flow obtained when the datalatch signal DL is changed from “L” to “H”. Both the PMOS transistor P2of the buffer B1 and the NMOS transistor N11 of the buffer B2 are turnedon. Therefore, neither of the diodes D35 and D36 added to the component32 a according to the first embodiment contribute to a current path.Accordingly, the current path is the same as in the first embodiment.

FIG. 32 is a circuit diagram corresponding to FIG. 16 and shows acurrent flow obtained when the data latch signal DL is changed from “H”to “L”. Since the diode D35 is reversibly biased, it does not contributeto the current path, either. The diode D36 is connected in the samedirection in parallel with the protective diode D44 in the input stageof the buffer B2. Therefore, a difference is made only in that the diodeD36 is added to a discharging current path in parallel with theprotective diode D44.

A second electric charge erasing period is started and the clock signalCLK, the data latch signal DL and the drive data are forcedly set to “L”also at the time t4 successively to the write discharge period.Accordingly, the capacitor C3 is discharged in the same manner as forthe electric charge erasing period according to the first embodiment.

In a case where an electric potential on the terminal E1 is charged morehighly than that on the terminal E2 in the capacitor C3, the sameoperation as that for the first electric charge erasing period shown inFIG. 30 is performed. On the other hand, FIG. 33 is a circuit diagramshowing a discharge path obtained when the electric potential on theterminal E1 is charged more highly than that on the terminal E2 in thecapacitor C3, which corresponds to FIG. 18. The discharge path is thesame as in FIG. 18.

After the discharge of the capacitor C3, the clock signal CLK, the datalatch signal DL and the drive data are forcedly set to “H” at a time t7prior to the time t5 that the sustain discharge period is started. Thereason is that the second common potential point 28 should rapidly risebecause it supplies the first HV potential for the sustain dischargeperiod.

E. Fourth Embodiment

A fourth embodiment will describe a technique in which the component 32c shown in the third embodiment is deformed. FIG. 34 is a circuitdiagram showing a structure of a component 32 d. The component 32 a isreplaced by the component 32 d to constitute the part 32 of theisolation circuit 23.

The component 32 d is different only in that it applies a second 5Vpotential to the buffer B2 to which the electric potential W_(—)5V isapplied in the component 32 c. More specifically, while an electricpotential is applied to a diode D33 in the same manner as in the firstembodiment, the second 5V potential is always applied to the buffer B2.Accordingly, it is possible to relieve an output load of the powercontrol circuit 24 for applying the electric potential W_(—)5V to boththe diode D33 and the buffer B2.

An operating sequence employed in the present embodiment is identical tothe operating sequence according to the third embodiment shown in FIG.27. Operation according to the present embodiment will be describedbelow by attaching importance to differences. FIGS. 35 and 36 arecircuit diagrams showing the operation to be performed for a writepreparation period according to the present embodiment, and correspondto FIGS. 28 and 29 respectively. A charging and discharging current ofthe capacitor C3 for the write preparation period according to thepresent embodiment is almost the same as that in the third embodiment.As shown in FIG. 36, in the case where the second common potential point28 supplies the first common potential, a difference is made in that thecurrent I96 does not pass through the cathode of the protective diodeD43 because the second 5V potential is supplied thereto.

FIG. 37 is a circuit diagram showing a path for a discharging current ofthe capacitor C3 for the first electric charge erasing period and thesecond electric charge erasing period obtained in a case where theterminal E1 of the capacitor C3 is charged more highly than the terminalE2 in the present embodiment. FIG. 38 is a circuit diagram showing apath for the discharging current of the capacitor C3 for the secondelectric charge erasing period in a case where the terminal E2 of thecapacitor C3 is charged more highly than the terminal E1 in the presentembodiment. FIGS. 37 and 38 correspond to FIGS. 30 and 33 according tothe third embodiment respectively, and illustrate almost the same pathsfor the discharging current as those in FIGS. 30 and 33. As shown inFIG. 38, a difference is made in that the protective diode D43 does notact as a discharging path because the second 5V potential is supplied toa cathode thereof for the second electric charge erasing period in whichthe terminal E2 of the capacitor C3 is charged more highly than theterminal E1.

FIGS. 39 and 40 correspond to FIGS. 31 and 32 respectively, and show acurrent flow obtained when a data latch signal DL is changed from “L” to“H” and from “H” to “L” for a write discharge period. For the writedischarge period, the second 5V potential is supplied to the electricpotential W_(—)5V. Therefore, a substantial current flow is notdifferent from that in the third embodiment. A difference is made onlyin that a current flowing in the protective diode D43 flows to a second5V power source without passing through a diode D21 when the data latchsignal DL is changed from “L” to “H” (FIG. 39). Furthermore, adifference is made only in that a current is supplied from the second 5Vpower source without passing through the PMOS transistor P1 of the powercontrol circuit 24 when the data latch signal DL is changed from “L” to“H” (FIG. 40).

F. Fifth Embodiment

FIG. 41 is a timing chart showing operation according to a fifthembodiment. In the fifth embodiment, an electric charge erasing periodof the capacitor C3 is performed at the beginning of a write dischargeperiod (times t8 to t10) in the circuits used in the first to fourthembodiments. The scan electrode Y_(k) first takes a scan potential−V_(SC) at the time t8, and first takes an electric potential Va at thetime t10. At the time t8, the H side of the common control signal, the Hside of the first power control signal and the second power controlsignal have already been set to “L”, “H” and “H”, respectively. Afterthe time t8, consequently, the second common potential and electricpotentials W_(—)5V and W_HV take the first common potential (groundpotential), the second 5V potential and the second HV potential,respectively.

In any of the first to fourth embodiments, drive data, the clock signalCLK and the data latch signal DL are forcedly set to “L” and the outputenable signal EN is forcedly set to “H” immediately before a time t3(that is, after the time t6 even in the third and fourth embodiments).In the present embodiment, the drive data, the clock signal CLK and thedata latch signal DL are forcedly set to “H” at the time t8, areforcedly set to “L” at a time t9 and become active at the time t10.

FIG. 42 is a circuit diagram showing operation to be performed at thetimes t8 to t9 according to the present embodiment for the circuit shownin the third embodiment. When the data latch signal DL is set to “H” atthe time t8 (so are the drive data and the clock signal CLK), the PMOStransistor P2 and the NMOS transistor N8 in the buffer B1 are turned onand off, respectively. Furthermore, the PMOS and NMOS transistors P1 andN1 of the power control circuit 24 have already been on and off,respectively.

In a case where the terminal E2 is charged to have a higher electricpotential than the electric potential on the terminal E1 in thecapacitor C3 before the time t8, the electric potential on the terminalE2 of the capacitor C3 performs step-up to exceed 5V at the time t8.Consequently, a discharging current flows toward the second 5V powersource through a parallel connection of diodes D33 and D43 and the diodeD21. On the other hand, the first 5V potential is supplied to theterminal E1 through the PMOS transistor P2. The circuit shown in thefirst embodiment also has the same path. In the circuits according tothe second and fourth embodiments, the discharging current flows in theprotective diode D43 without passing through the diode D21.

Since the second common potential point 28 takes the first commonpotential, the protective diode D44 or, furthermore, the diode D36 isreversibly biased. Accordingly, an electric potential of 5V is appliedfor the first common potential on both the terminals E1 and E2 of thecapacitor C3 so that a discharge is performed.

In a case where the terminal E1 is charged to have a higher electricpotential than the electric potential on the terminal E2 in thecapacitor C3 before the time t8, 5V is not exceeded even if the electricpotential on the terminal E2 of the capacitor C3 performs the step-up.Therefore, the discharge shown in FIG. 42 is not caused. In the casewhere such charging is performed, the capacitor C3 is discharged at thetimes t9 to t10.

FIG. 43 is a circuit diagram showing operation performed at the times t9to t10 in the present embodiment for the circuit shown in the thirdembodiment. At the times t9 to t10 in the present embodiment, when thedata latch signal DL is set to “L” at the time t9 (so are the drive dataand the clock signal CLK), the PMOS transistor P2 and the NMOStransistor N8 are turned off and on in the buffer B1, respectively.Differently from the first electric charge erasing period according tothe third embodiment, the electric potential W_(—)5V takes the second 5Vpotential. However, since the diodes D33 and D43 are reversibly biased,they cannot act as paths for a discharging current. In this case,accordingly, a discharge is the same as the operation to be performedfor the first electric charge erasing period according to the thirdembodiment shown in FIG. 30.

G. Sixth Embodiment

A sixth embodiment will describe a technique in which the component 32 ashown in the first embodiment is deformed. FIG. 44 is a circuit diagramshowing a structure of a component 32 e. A capacitor is not used for anisolation in the component 32 e. The component 32 a is replaced by thecomponent 32 e to constitute the part 32 of the isolation circuit 23.

In the component 32 e, for example, the data latch signal DL which isobtained from the digital signal generating circuit 21 is input to thebuffer B1 (so are the clock signal CLK and one bit of drive data), andthe output terminal of the buffer B1 is connected to an anode of a diodeD61. Electric potentials are supplied from the first common potentialpoint 27 and the first 5V power source to the buffer B1, respectively.

A cathode of the diode D61 is connected to the input terminal of thebuffer B2 and one of terminals of a resistor R6 in common. The second 5Vpower source is connected to the power terminal of the buffer B2, andthe second common potential point 28 is connected to the common terminalof the buffer B2 in common with the other terminal of the resistor R6.

In operation according to the present embodiment, therefore, the powercontrol circuit 24 is not required and an electric charge erasing periodfor the capacitor C3 is not necessary.

FIG. 45 is a timing chart showing the operation according to the presentembodiment. The operation in the timing chart is different from theoperation according to the first embodiment shown in FIG. 12 in thatdrive data, the clock signal CLK and the data latch signal DL may be “H”or “L” (undefined) in an inactive state.

The operation to be performed for a write preparation period will bedescribed below by attaching importance to differences between thepresent embodiment and the first embodiment. FIGS. 46 and 47 are circuitdiagrams showing a current flowing when the second common potential ischanged at times tl and t2, and correspond to FIGS. 13 and 14respectively.

After the time t1, the current I92 flows to charge the address electrodeA_(j) in the same manner as in the first embodiment. For example, evenif the data latch signal DL is any of “H” and “L”, the cathode of thediode D61 is connected to the first HV power source through the resistorR6, the second common potential point 28 and the NMOS transistor N4 onthe high arm side of the power control circuit 26. Therefore, the diodeD61 is reversibly biased. Accordingly, even if the second commonpotential is raised, the current I93 shown in the first embodiment doesnot flow but the component 32 e is isolated from a fluctuation in thesecond common potential.

After the time t2, electric charges stored in the address electrodeA_(j) are discharged to the first common potential point 27 through theNMOS transistor N10 on the low arm side of the drive circuit 22 _(i) andthe NMOS transistor N5 on the low arm side of the power control circuit26 or the protective diode D45 on the high arm side of the drive circuit22 _(i) and the NMOS transistor N3 on the low arm side of the powercontrol circuit 25 in the same manner as in the first embodiment.

If a level input to the buffer B1 is “H”, the diode D61 is forwardbiased so that a forward current I61 flows. By limiting the magnitude ofthe forward current I61 by means of the resistor R6, the component 32 ecan be isolated from the fluctuation in the second common potential. Itis apparent that the current I61 does not flow but the above-mentionedisolation can be performed if the level input to the buffer B1 is “L”.

A write discharge sequence is the same as in the first embodiment. FIG.48 corresponds to FIG. 15 showing the first embodiment, and is a circuitdiagram showing a current flow obtained when the data latch signal DL ischanged from “L” to “H”, for example.

While the NMOS transistors N4 and N5 of the power control circuit 26 areturned off and on respectively, the PMOS transistor P2 and the NMOStransistor N8 of the buffer B1 are turned on and off respectively.Therefore, a current flows from the first 5V power source through thePMOS transistor P2, the diode D61, the resistor R6, the second commonpotential point 28 and the NMOS transistor N5. By a voltage drop of theresistor R6, an electric potential on the input terminal of the bufferB2 is set to “H” and a level “H” is transmitted.

In this case, a microcurrent I71 flows so that a gate electrode of theNMOS transistor N11 is charged.

FIG. 49 corresponds to FIG. 16 showing the first embodiment, and is acircuit diagram illustrating a current flow obtained when the data latchsignal DL is changed from “L” to “H”, for example.

The PMOS transistor P2 and the NMOS transistor N8 of the buffer B1 areturned off and on, respectively. Therefore, the diode D61 is reversiblybiased so that less current flows. Accordingly, a voltage drop is notcaused in the resistor R6 but the first common potential (groundpotential) is applied to the buffer B2 through the second commonpotential point 28 and a level “L” is transmitted.

The gate electrode of the NMOS transistor N1 which is charged as shownin FIG. 48 is discharged through the resistor R6. Accordingly, atransition speed of the level depends on an input capacity of the bufferB2 and the resistor R6. Therefore, it is desirable that a value of theresistor R6 should be set according to a frequency of an input signal.

While the output enable signal EN is set to “H” and is brought into aninactive state for a sustain discharge period in the present embodiment,the drive data, the clock signal CLK and the data latch signal DL may beundefined in the same manner as for the write preparation period. Thereason is that the capacitor C3 does not need to be discharged.

H. Seventh Embodiment

In the first to fifth embodiments, in the case where the level of thesignal input to the buffer B1 is changed from “L” to “H” to dischargethe capacitor C3 (FIGS. 15, 22, 31, 39 and 48), the first 5V potentialis supplied from the output terminal of the buffer B1, while the secondcommon potential is equal to the first common potential. Therefore, thesecond 5V potential which is equal to the first 5V potential is alsoapplied to the cathodes of the diodes D33 and D43. Accordingly, theelectric potential on the terminal E2 of the capacitor C3 is higher thanthat on the terminal E1 by a forward voltage supported by the diodes D21and D33 (or furthermore D43), and the terminal E2 of the capacitor C3 isslightly charged correspondingly. The present embodiment will describe atechnique in which such a slight charge is also avoided.

FIG. 50 is a circuit diagram showing a structure of a voltage source forsupplying an electric potential onto the high arm side of the powercontrol circuit 24, that is, to the source of the PMOS transistor P1. Ananode of a diode D8 is connected to the second 5V power source, and acapacitor C4 is connected between a cathode of the diode D8 and thesecond common potential point 28. An electric potential is supplied froma node of the capacitor C4 and the cathode of the diode D8 to the sourceof the PMOS transistor P1. The circuit is designed such that a forwardvoltage of the diode D8 is the sum of forward voltages of the diodes D21and D33.

An electric potential which is lower than the second 5V potential by theforward voltage of the diode D8 is supplied to the source of the PMOStransistor P1. Therefore, the electric potential on the terminal E2 ofthe capacitor C3 is reduced down to the second 5V potential, that is,the first 5V potential so that the capacitor C3 can completely bedischarged. A discharging current flowing in this case, for example, thecurrent I102 shown in FIG. 15 flows to the second electric potentialpoint 28 through the capacitor C4.

In the operation according to the present embodiment, the second commonpotential is equal to the first common potential. Therefore, the firstcommon potential point 27 may be connected to the capacitor C4 and thefirst 5V potential may be connected to the anode of the diode D8.

I. Eighth Embodiment

FIG. 51 is a circuit diagram showing a relationship between the drivecircuit 22 _(i) and various signals given thereto through the isolationcircuit 23. For example, in order to cope with a VGA specification,thirty drive circuits 22 _(i) are required as described in the firstembodiment. Two control signals other than the output enable signal ENtransmitted through the photocoupler PC in the part 31, that is, theclock signal CLK and the data latch signal DL are transmitted throughthe capacitor C3 in the part 32. These control signals are transmittedto each of the drive circuits 22 _(i) in common, and 4-bit drive data DT(1) to DT (n) are transmitted to each of the drive circuits 22 _(i)through the capacitor C3 in parallel. Finally, the number of thecomponents 32 a (or 32 b to 32 e) to be required is 30×4+2=122 in orderto cope with the VGA specification. However, the number can be reducedas follows.

FIG. 52 is a circuit diagram showing the case where the drive circuit 22_(i) has a serial input-output shift register built therein, and FIG. 53is a timing chart showing a state in which drive data is input in thecircuit of FIG. 52 (a delay in the isolation circuit 23 is ignored).

A 4-bit data output of an odd-numbered drive circuit 22 _((2s−1)) isgiven to a 4-bit data input of an even-numbered drive circuit 22 _(2s)(s=1, 2, . . . z; z=n/2 if n is an even number, and z=(n−1)/2 if n is anodd number. In FIG. 52, n is an even number.) Since the drive circuit 22_(i) has the serial input-output shift register, the 4-bit data inputgiven thereto is output (shifted out) as its own data outputsynchronously with a rise (or fall) of the clock signal CLK. μPD16327manufactured by NEC has such a register built therein.

Accordingly, 4-bit drive data DT (2s) for the even-numbered drivecircuit 22 _(2s) and 4-bit drive data DT (2s−1) for the odd-numbereddrive circuit 22 _((2s−1)) are sequentially given to a 4-bit data inputfor the odd-numbered drive circuit 22 _((2s−1)). Also in order to copewith the VGA specification, the number of the components 32 a to berequired is 30×4/2+2=62.

Of course, the number of the drive circuits 22 _(i) for transferring4-bit data by the serial input-output shift register of the drivecircuit 22 _(i) is not restricted to two but can be generally set to L(≧2). If L is greater, a frequency of the clock signal CLK should beincreased (to L/2 times or more as high as the frequency of the datalatch signal DL). It is desirable that a capacitance of the capacitor C3in the component 32 a (or 32 b to 32 d) should be small in order toshorten charging and discharging periods to increase isolation effects.If the capacitance of the capacitor C3 is small, operation is morestabilized during transfer if a frequency of a signal to be transferredthrough the capacitor C3 is higher. In respect of the operation of theisolation circuit 23, accordingly, it is desirable that L should beincreased to raise the frequency of the clock signal CLK.

However, the number of the components 32 a (or 32 b to 32 e) can furtherbe reduced with the frequency of the clock signal CLK kept as it is.FIG. 54 is a circuit diagram showing the case where a set of four drivecircuits 22 _(i) receive drive data transfer, and FIG. 55 is a timingchart showing a state in which the drive data is input in the circuit ofFIG. 54 (a delay in the isolation circuit 23 is ignored).

The serial input-output shift register operates synchronously with therise (or fall) of the clock signal CLK. Therefore, if L=2 is set, forexample, the highest frequency of a signal to be transferred in theisolation circuit 23 is ½ of the frequency of the clock signal CLK. Aninverted signal bar CLK of the clock signal CLK is generated, and a4-bit input is time-shared by a pair of drive circuits 22 _(i) (forexample, drive circuits 22 ₁ and 22 ₂) in which the drive data isshifted by the clock signal CLK and a pair of drive circuits 22 _(i)(for example, drive circuits 22 ₃ and 22 ₄) in which the drive data isshifted by the inverted signal bar CLK.

First of all, 4-bit drive data DT (2) for the drive circuit 22 ₂ istransferred as a first data input to the isolation circuit 23. The drivedata is shifted from the drive circuit 22 ₁ to the drive circuit 22 ₂synchronously with the rise of the clock signal CLK at a time τ1. Next,4-bit drive data DT (4) for the drive circuit 22 ₂ is transferred as thefirst data input to the isolation circuit 23, and is shifted from thedrive circuit 22 ₃ to the drive circuit 22 ₄ synchronously with the riseof the inverted signal bar CLK at a time τ2. Furthermore, 4-bit drivedata DT (1) for the drive circuit 22 ₁ is transferred as the first datainput to the isolation circuit 23 at a time τ3, and a first data latchsignal DL1 is set to “H” before a time τ4 at which the clock signal CLKrises so that the 4-bit drive data DT (1) and DT (2) are latched ontothe drive circuits 22 ₁ and 22 ₂, respectively. At a time τ5furthermore, the 4-bit drive data DT (3) for the drive circuit 22 ₃ istransferred to the isolation circuit 23. Then, a second data latchsignal DL2 is set to “H” before a time τ6 at which the inverted signalbar CLK rises. Consequently, the 4-bit drive data DT (3) and DT (4) arelatched onto the drive circuits 22 ₃ and 22 ₄, respectively.

Referring to a second data input, similarly, 4-bit drive data DT (6) fora drive circuit 22 ₆, 4-bit drive data DT (8) for a drive circuit 22 ₈,4-bit drive data DT (5) for a drive circuit 22 ₅ and 4-bit drive data DT(7) for a drive circuit 22 ₇ are transferred in this order.

In the VGA specification, the number of the drive circuits 22 _(i) isthirty, the number of 4-bit inputs required for the drive circuits 22 ₁to 22 ₂₈ is 28/4=7, and the number of 4-bit inputs required for thedrive circuits 22 ₂₉ and 22 ₃₀ is one. Therefore, (8×4=32) components 32a (or 32 b to 32 e) are required for the drive data. Furthermore, sincethe component 32 a is required for the clock signal CLK and the firstand second data latch signals DL1 and DL2 which act as the controlsignals (the inverted signal bar CLK may take inversion of the clocksignal CLK transferred through the isolation circuit 23), thirty-fivecomponents 32 a are finally enough.

While the present invention has been described in detail, the abovedescription is illustrative in all aspects and the present invention isnot restricted thereto. It will be understood that numerous variantswhich are not illustrated can be supposed without departing from thescope of the invention.

What is claimed is:
 1. An apparatus for driving an address electrode fora surface discharge type plasma display panel having a plurality of scanelectrodes, a plurality of address electrodes which are orthogonal tothe scan electrodes, and a display cell formed on each of intersectingpoints of the scan electrodes and the address electrodes, comprising: aplurality of drive circuits including a first number of output stages,each output stage having an output terminal provided corresponding toeach of the address electrodes and connected thereto, and a first inputterminal and a second input terminal, one of which is selectivelyconnected to the output terminal; a first power control circuit forsupplying, to the second input terminal, one of a reference potentialand a first electric potential which is higher than the referencepotential; and a second power control circuit for supplying, to thefirst input terminal, a second electric potential which is lower thanthe first electric potential and is higher than the reference potentialor connecting the first input terminal to the second input terminal. 2.The address electrode driving apparatus according to claim 1, furthercomprising: a control circuit for outputting drive data which serves toset the output terminal of the drive circuit to be connected to thefirst input terminal or the second input terminal, and a plurality oftransmitting circuits provided corresponding to each of the addresselectrodes for transmitting the drive data for the corresponding addresselectrodes, each of the transmitting circuits including: a first bufferhaving an input terminal for inputting the drive data and an outputterminal for transmitting the drive data, being connected to a firstreference potential point for supplying the reference potential and afirst electric potential point for supplying a first source potentialwhich is higher than the reference potential and is lower than thesecond electric potential, and receiving operating power therefrom; acapacitor having one of terminals connected to the output terminal ofthe first buffer and the other terminal, and a second buffer having aninput terminal connected to the other terminal of the capacitor and anoutput terminal connected to a corresponding one of the drive circuits,being connected to the second input terminal and a second electricpotential point, and receiving operating power therefrom.
 3. The addresselectrode driving apparatus according to claim 2, wherein each of thedrive circuits further includes: a protective diode having a cathodeconnected to a corresponding one of the address electrodes and an anodeconnected to the second input terminal.
 4. The address electrode drivingapparatus according to claim 3, comprising a third electric potentialpoint to be connected to one of a fourth electric potential point towhich a second source potential is supplied and the second inputterminal, each of the transmitting circuits including: a first diode ananode connected to the first reference potential point and a cathodeconnected to the terminal of the capacitor; and a second diode having ananode connected to the other terminal of the capacitor and a cathodeconnected to the third electric potential point, and the second bufferfurther including: a protective diode having a cathode connected to theother terminal of the capacitor and an anode connected to the secondinput terminal.
 5. The address electrode driving apparatus according toclaim 4, wherein the second electric potential point is the thirdelectric potential point.
 6. The address electrode driving apparatusaccording to claim 4, wherein the second electric potential point is theforth electric potential point.
 7. The address electrode drivingapparatus according to claim 4, wherein each of the transmittingcircuits further includes: a third diode having an anode connected tothe terminal of the capacitor and a cathode connected to the firstelectric potential point, and a fourth diode having an anode connectedto the second input terminal and a cathode connected the other terminalof the capacitor.
 8. The address electrode driving apparatus accordingto claim 7, wherein the second electric potential point is the thirdelectric potential point.
 9. The address electrode driving apparatusaccording to claim 7, wherein the second electric potential point is thefourth electric potential point.
 10. The address electrode drivingapparatus according to claim 4, wherein the first buffer furtherincludes a protective diode having an anode connected to the terminal ofthe capacitor and a cathode connected to the first electric potentialpoint.
 11. The address electrode driving apparatus according to claim 4,further comprising: a diode having an anode connected to the fourthelectric potential point and a cathode; and a capacitor connectedbetween the cathode of the diode and a second reference potential pointacting as a reference of a second source potential to be applied to thefourth electric potential point, wherein the third electric potentialpoint is connected to the fourth electric potential point through thediode.
 12. The address electrode driving apparatus according to claim 2,further comprising: a control circuit for outputting drive data whichserves to set the output terminal of the drive circuit to be connectedto the first input terminal or the second input terminal; and aplurality of transmitting circuits provided corresponding to each of theaddress electrodes for transmitting the drive data for the correspondingaddress electrodes, each of the transmitting circuits including: a firstbuffer having an input terminal for inputting the drive data and anoutput terminal for transmitting the drive data, being connected to afirst reference potential point for supplying the reference potentialand a first electric potential point for supplying a first sourcepotential which is higher than the reference potential and is lower thanthe second electric potential, and receiving operating power therefrom;a diode having an anode connected to the output terminal of the firstbuffer and a cathode; and a second buffer having an input terminalconnected to the cathode of the diode and an output terminal connectedto a corresponding one of the drive circuits, being connected to thesecond input terminal and a second electric potential point, andreceiving operating power therefrom.
 13. The address electrode drivingapparatus according to claim 12, wherein each of the transmittingcircuits further includes a resistor provided between the cathode of thediode and the second input terminal.
 14. The address electrode drivingapparatus according to claim 2, wherein the drive circuits furtherinclude a second number of data input terminals for inputting the secondnumber of drive data, and the second number of data output terminals forshifting out data given to the data input terminals, and a third numberof drive circuits make a set and are connected in series with respect tothe data input terminals and the data output terminals.
 15. The addresselectrode driving apparatus according to claim 14, wherein the set ofdrive circuits have a timing in which the drive data is shifted out fromthe data input terminal to the data output terminal and a timing inwhich the drive data given to the data input terminal is latched, thetimings being divided into two classes which are different from eachother.
 16. The address electrode driving apparatus according to claim 1,wherein the surface discharge type plasma display panel further includesa plurality of other scan electrodes which are orthogonal to the addresselectrodes, and a predetermined electric potential is applied to thescan electrodes through a pair of diodes connected in antiparallel witheach other.
 17. An address electrode driving method for a surfacedischarge type plasma display panel, for a plasma display systemcomprising: a surface discharge type plasma display panel including aplurality of scan electrodes, a plurality of address electrodes whichare orthogonal to the scan electrodes, and a display cell formed on eachof intersecting points of the scan electrodes and the addresselectrodes; a plurality of drive circuits including a first number ofoutput stages, each output stage having an output terminal providedcorresponding to each of the address electrodes and connected thereto,and a first input terminal and a second input terminal, one of which isselectively connected to the output terminal; a plurality of drivecircuits provided corresponding to the address electrodes, each of whichhas an output terminal connected to a corresponding one of the addresselectrodes and a first input terminal and a second input terminal, oneof which is selectively connected to the output terminal; a controlcircuit for outputting drive data which serves to set the outputterminal of the drive circuit to be connected to the first inputterminal or the second input terminal; a first power control circuit forsupplying, to the second input terminal, one of a reference potentialand a first electric potential which is higher than the referencepotential; a second power control circuit for supplying, to the firstinput terminal, a second electric potential which is lower than thefirst electric potential and is higher than the reference potential, orfor connecting the first input terminal to the second input terminal; afirst buffer having an input terminal provided corresponding to theaddress electrodes for inputting the drive data for the correspondingaddress electrodes, an output terminal for transmitting the drive data,and an output stage having a push-pull structure which is connected inseries between a first reference potential point for supplying thereference potential and a first electric potential point for supplying afirst source potential which is higher than the reference potential andis lower than the second electric potential; a capacitor having one ofterminals connected to the output terminal of the first buffer and theother terminal; a second buffer an input terminal connected to the otherterminal of the capacitor, an output terminal connected to acorresponding one of the drive circuits, and an input stage having apush-pull structure which is connected in series between the secondinput terminal and a second electric potential point; a first diodehaving an anode connected to the first reference potential point and acathode connected to the terminal of the capacitor; and a second diode acathode connected to the second electric potential point and an anodeconnected to the other terminal of the capacitor, the method comprisingthe steps of: for a write preparation period, connecting the secondelectric potential point to the second input terminal; connecting thefirst input terminal to the second input terminal by the second powercontrol circuit; and supplying the first electric potential to thesecond input terminal by the first power control circuit, and thensupplying the reference potential, for a write discharge period,connecting the second input terminal to the first reference potentialpoint by the first power control circuit; supplying the first sourcepotential to the second electric potential point; supplying the secondelectric potential to the first input terminal by the second powercontrol circuit; and connecting an output terminal of each of the drivecircuits to one of the first input terminal and the second inputterminal based on the drive data, and after the write discharge periodand before a sustain discharge period, connecting the second inputterminal to the first reference potential point by the first powercontrol circuit; connecting the second electric potential point thesecond input terminal; connecting the first input terminal to the secondinput terminal by the second power control circuit; and forcedly settingthe drive data to a reference potential.
 18. The address electrodedriving method according to claim 17, further comprising the step of:(a-4) forcedly setting the drive data to “H” prior to the step (a-3) forthe write preparation period.
 19. The address electrode driving methodaccording to claim 18, further comprising the step of: (d) forcedlysetting the drive data to “L” after the write preparation period andbefore the write discharge period.
 20. An address electrode drivingmethod, for a plasma display system comprising: a surface discharge typeplasma display panel including a plurality of scan electrodes, aplurality of address electrodes which are orthogonal to the scanelectrodes, and a display cell formed on each of intersecting points ofthe scan electrodes and the address electrodes; a plurality of drivecircuits including an output terminal provided corresponding to each ofthe address electrodes and connected to a corresponding one of theaddress electrodes, and a first input terminal and a second inputterminal, one of which is selectively connected to the output terminal;a control circuit for outputting drive data which serves to set theoutput terminal of the drive circuit to be connected to the first inputterminal or the second input terminal; a first power control circuit forsupplying one of a reference potential and a first electric potentialwhich is higher than the reference potential to the second inputterminal; and a second power control circuit for supplying, to the firstinput terminal, a second electric potential which is lower than thefirst electric potential and is higher than the reference potential orconnecting the first input terminal to the second input terminal, afirst buffer having an input terminal provided corresponding to each ofthe address electrodes for inputting the drive data for thecorresponding address electrodes, an output terminal for transmittingthe drive data, and an output stage having a push-pull structure whichis connected in series between a first reference potential point forsupplying the reference potential and a first electric potential pointfor supplying a first source potential that is higher than the referencepotential and is lower than the second electric potential; a diodehaving an anode connected to the output terminal of the first buffer anda cathode; a second buffer having an input terminal connected to thecathode of the diode, an output terminal connected to a correspondingone of the drive circuits, and an input stage having a push-pullstructure which is connected in series between the second input terminaland a second electric potential point; and resistor connected to thesecond input terminal and the input terminal of the second buffer, themethod comprising the steps of: (a) for a write preparation period,(a-1) connecting the first input terminal to the second input terminalby the second power control circuit; and (a-2) supplying the firstelectric potential to the second input terminal by the first powercontrol circuit, and then supplying the reference potential; (b) for awrite discharge period, (b-1) connecting the second input terminal tothe first reference potential point by the first power control circuit;(b-2) supplying the second electric potential to the first inputterminal by the second power control circuit; and (b-3) connecting theoutput terminals of the drive circuits to one of the first inputterminal and the second input terminal based on the drive data, and (c)after the write discharge period and before a sustain discharge period,(c-1) connecting the second input terminal to the first referencepotential point by the first power control circuit; and (c-2) connectingthe first input terminal to the second input terminal by the secondpower control circuit.